Processor and program execution method capable of efficient program execution

1. A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the plurality of programs, the processor comprising:

a plurality of register groups;

a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the execution target register group every time a first predetermined period elapses; and

a restoring unit operable to restore, every time the switching is performed, one of the plurality of register value groups into one of the plurality of register groups that is not selected as the execution target register group;

a saving unit operable to save, prior to the restoring, register values in the one of the plurality of register groups targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and

a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group, wherein

the first predetermined period is a time period that is identified via a timeslot indicating a program execution timeframe which is defined so that time periods for occupying the program execution unit are allotted to programs in accordance with respective processing periods of the programs,

the restoring unit, in order to switch between timeslots which are program execution timeframes, periodically in a predetermined order:

refers to information specifying a timeslot that is a present execution target and a timeslot that is to become a next execution target;

identifies the timeslot that is to become the next execution target;

obtains a program execution timeframe allotted to the identified timeslot; and

determines a register value group which is to be a restore target, based on a candidate register value group allotted to the identified timeslot.

2. The processor of claim 1 , further comprising:

a first detecting unit operable to detect an occurrence of a suspend-cause that results in the program execution being suspended;

a second detecting unit operable to detect a cancellation of the suspend-cause, and

a power-consumption reducing unit operable to reduce a power consumption of hardware for executing programs, wherein

when the occurrence of a suspend-cause relating to a program for execution is detected, the program execution unit relinquishes, until the suspend-cause is cancelled, an execution period to be allotted for execution of the program, and

the power-consumption reducing unit performs the reducing for a duration that the relinquishing is performed.

3. The processor of claim 2 , wherein

the program execution unit has a CPU for executing programs, and

the power-consumption reducing unit performs the reducing for the duration that the relinquishing is performed by reducing a voltage applied to the CPU or setting the voltage to zero.

4. The processor of claim 2 , further comprising:

a receiving unit for receiving an execution request for a program that is to be executed non-steadily, wherein

the power-consumption reducing unit stops the reducing if the reducing is being performed when the execution request is received.

5. The processor of claim 4 , wherein

the execution request is an interrupt-processing request.

6. The processor of claim 4 , wherein

the execution request is an event-processing request for urgently executing a program following an exceptional switching by the select/switch unit.

7. The processor of claim 2 , wherein

the program execution unit has a CPU for executing programs, and

the power-consumption reducing unit performs the reducing for the duration that the relinquishing is performed by blocking a clock signal supplied to the CPU.