IP Library Granted Patent US 8,629,453
Granted Patent B2
US 8,629,453 · App. 12/110,816 · Granted Jan 14, 2014

Externally configurable integrated circuits

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Quick Facts
Patent No.
US 8,629,453
App. No.
12/110,816
Granted
Jan 14, 2014
Kind
B2
Abstract

A die comprising two or more active electronic components is provided. The active electronic components are capable of being interconnected using interconnections external to the die. The die may be encased within a package, and the active electronic components may be interconnected using interconnections external to the package. By interconnecting the active electronic components, either directly or through one or more additional components, a desired circuit may be formed. In some examples, the desired circuit may be a monolithic microwave integrated circuit (MMIC). Methods of forming the circuit are also disclosed.

Claims (29)

1. A device comprising:

a die comprising:

a first individual active electronic element;

a second individual active electronic element;

wherein the first individual active electronic element and the second individual active electronic element are not electrically interconnected to another electronic element by interconnections on the die;

wherein the first individual active electronic element and the second individual active electronic element are configured to be interconnected via external interconnections;

wherein the die does not include a passive electronic element.

2. The device of claim 1 , wherein the first individual active electronic element and the second individual active electronic element are configured to be directly interconnected via external interconnections external to the die.

3. The device of claim 1 , wherein the first individual active electronic element and the second individual active electronic element are interconnected to form at least part of a monolithic microwave integrated circuit (MMIC).

4. The device of claim 1 , wherein the first individual active electronic element is formed in a gallium nitride material, and the second individual active electronic element is formed in the gallium nitride material.

5. The device of claim 4 , wherein the first individual active electronic element and the second individual active electronic element are disposed in an approximately mirror configuration on the die.

6. The device of claim 4 , wherein the first individual active electronic element is a transistor.

7. The device of claim 6 , wherein the first individual active electronic element is a first field effect transistor (FET).

8. The device of claim 1 , further comprising a first passive electronic element formed external to the die and electrically connected to the first individual active electronic element.

9. The device of claim 8 , further comprising a second passive electronic element formed external to the die and electrically connected to the second active electronic element.

10. The device of claim 1 , further comprising an interconnection, external to the die, interconnecting the first individual active electronic element and the second individual active electronic element.

11. A method of fabricating a device, comprising:

forming a first individual active electronic element and a second individual active electronic element on a die, the first and second individual active electronic element not interconnected to another electronic element by internal interconnections and the die not including a passive electronic element;

wherein the first and second individual electronic elements are configured to accept interconnections external to the die.

12. The method of claim 11 , wherein forming the first individual active electronic element comprises forming the first individual active electronic element in a gallium nitride material.

13. The method of claim 12 , wherein forming the die comprises forming the gallium nitride material on a substrate.

14. The method of claim 11 , further comprising interconnecting the first individual active electronic element and the second individual active electronic element via an interconnection external to the die.

15. A method of constructing a monolithic microwave integrated circuit (MMIC), comprising:

interconnecting, externally to a die, a first individual active electronic element formed in a gallium nitride material on the die and a second individual active electronic element formed in the gallium nitride material on the die to form a MMIC on the die, the MMIC comprising the first individual active electronic element, the second individual active electronic element not interconnected to another electronic component by internal interconnections, and the die not including a passive electronic element.

16. The method of claim 15 , wherein the first individual active electronic element is a first transistor and the second individual active electronic element is a second transistor, and wherein interconnecting the first individual active electronic element and the second individual active electronic element comprises connecting a metal between a first contact pad of the first transistor and a second contact pad of the second transistor.

17. The method of claim 16 , wherein connecting a metal between the first contact pad of the first transistor and the second contact pad of the second transistor comprises wirebonding the first contact pad to the second contact pad.

18. The method of claim 16 , wherein interconnecting the first individual active electronic element and the second individual active electronic element further comprises coupling a passive electronic element external to the die between the first transistor and the second transistor.

19. The method of claim 16 , wherein interconnecting the first individual active electronic element and the second individual active electronic element comprises interconnecting the first transistor and the second transistor in a two-stage configuration.

20. The method of claim 16 , wherein the die is encased within a package, and wherein the metal is disposed at least partially external to the package.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: INFINEON TECHNOLOGIES AMERICAS CORP.
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 047908/0698 →
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
CONFIDENTIAL EXCLUSIVE LICENSE AND IP PURCHASE AGREEMENTS THAT RESTRICT PATENT ASSIGNMENT BY CURRENT OWNER (ONLY NON-CONFIDENTIAL, PUBLIC MATERIALS SUMMARIZING AGREEMENTS AND LITIGATION DISPUTES RELATING TO THE SAME ATTACHED) Recorded Nov 3, 2017
From: INTERNATIONAL RECTIFIER CORPORATION
To: NITRONEX LLC; MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 044532/0627 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2010
From: NITRONEX CORPORATION
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 024953/0770 →
RELEASE OF SECURITY INTEREST Recorded Aug 5, 2010
From: SILICON VALLEY BANK
To: NITRONEX CORPORATION
Reel/Frame 024794/0055 →
SECURITY AGREEMENT Recorded May 4, 2010
From: NITRONEX CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 024320/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2009
From: GELLER, BERNARD D.; SEARS, PETER C.
To: NITRONEX CORPORATION
Reel/Frame 023048/0550 →