PLL circuit with improved phase difference detection
View Patent ↗In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
1. A PLL circuit configured by a feedback loop comprising:
a phase frequency detector making comparison of phases and frequencies of a reference signal and a feedback signal;
a time to digital converter converting an output of the phase frequency detector into a digital value;
a digital loop filter removing a high frequency noise component from an output of the time to digital converter;
a digitally controlled oscillator controlled based on an output of the digital loop filter; and
a divider frequency-dividing an output of the digitally controlled oscillator and outputting the feedback signal,
wherein an offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0is inputted to the time to digital converter even when the PLL circuit is locked.
2. The PLL circuit according to claim 1 ,
wherein the time to digital converter comprises:
a first delay device having a first delay time; and
a plurality of second delay devices connected in latter stages of the first delay device and having second delay times shorter than the first delay time.
3. A PLL circuit configured by a feedback loop including:
phase detecting or frequency detecting and time-to-digital converting equipment making comparison of phases and frequencies of a reference signal and a feedback signal and converting a result of the comparison into a digital value;
a digital loop filter removing a high frequency noise component from an output of the phase detecting or frequency detecting and time-to-digital converting equipment;
a digitally controlled oscillator controlled based on an output of the digital loop filter; and
a divider frequency-dividing an output of the digitally controlled oscillator and outputting the feedback signal,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a counter measuring a phase difference between the reference signal and the feedback signal with first precision; and
a delay-line measuring the phase difference between the reference signal and the feedback signal with second precision finer than the first precision.
4. The PLL circuit according to claim 3 ,
wherein the divider comprises:
a first divider frequency-dividing the output of the digitally controlled oscillator and outputting a clock signal; and
a second divider frequency-dividing an output of the first divider and outputting the feedback signal,
wherein the clock signal is inputted as a clock of the counter.
5. The PLL circuit according to claim 3 , further comprising:
a third divider frequency-dividing the output of the digitally controlled oscillator and outputting a clock signal,
wherein the clock signal is inputted as a clock of the counter.
6. The PLL circuit according to claim 3 ,
wherein the output of the digitally controlled oscillator is inputted as a clock of the counter.
7. The PLL circuit according to claim 3 , further comprising:
a function of avoiding an error in combining phase differences of the counter and the delay-line by always measuring phase differences in at least two paths and adopting a phase difference judged to be no problem from a value of the delay-line.
8. The PLL circuit according to claim 4 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment further comprises:
control logic obtaining the phase difference based on measurement results of the counter and the delay-line; and
an offset circuit provided at a latter stage of the control logic, and
wherein a phase relation when the PLL circuit is locked is adjusted and phase comparison operation can be carried out in a period when a division ratio of the first divider is constant.
9. A PLL circuit configured by a feedback loop comprising:
phase detecting or frequency detecting and time-to-digital converting equipment making comparison of phases and frequencies of a reference signal and a feedback signal and converting a result of the comparison into a digital value;
a digital loop filter removing a high frequency noise component from an output of the phase detecting or frequency detecting and time-to-digital converting equipment;
a digitally controlled oscillator controlled based on an output of the digital loop filter; and
a divider frequency-dividing an output of the digitally controlled oscillator and outputting the feedback signal,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a first circuit converting a phase of the reference signal into digital;
a second circuit converting a phase of the feedback signal into digital; and
a subtractor obtaining a difference between outputs of the first circuit and the second circuit.
10. The PLL circuit according to claim 9 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment further comprises:
a latch using an output of the first circuit as a data input, using an output of the second circuit as a clock input and outputting a signal to the subtractor.
11. The PLL circuit according to claim 9 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment further comprises:
a latch using an output of the second circuit as a data input, using an output of the first circuit as a clock input and outputting a signal to the subtractor.
12. The PLL circuit according to claim 10 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a function of digitally expressing a time of 2π corresponding to 1 clock by holding a phase by the latch once and then obtaining a difference between held data and a signal inputted next.
13. The PLL circuit according to claim 10 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a function of making judgment of a polarity of a phase and adding a digital value corresponding to -2π according to the judgment.
14. The PLL circuit according to claim 10 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment further comprises:
a frequency judgment circuit; and
a function of responding when a frequency displaces largely.
15. The PLL circuit according to claim 11 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a function of digitally expressing a time of 2π corresponding to 1 clock by holding a phase by the latch once and then obtaining a difference between held data and a signal inputted next.
16. The PLL circuit according to claim 11 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment comprises:
a function of making judgment of a polarity of a phase and adding a digital value corresponding to -2π according to the judgment.
17. The PLL circuit according to claim 11 ,
wherein the phase detecting or frequency detecting and time-to-digital converting equipment further comprises:
a frequency judgment circuit; and
a function of responding when a frequency displaces largely.