IP Library Granted Patent US 7,977,799
Granted Patent B2
US 7,977,799 · App. 12/112,652 · Granted Jul 12, 2011

Planar packageless semiconductor structure with via and coplanar contacts

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Quick Facts
Patent No.
US 7,977,799
App. No.
12/112,652
Granted
Jul 12, 2011
Kind
B2
Abstract

A semiconductor device includes a substrate having a first side and a second side and an epitaxial layer disposed over the second side. The device also includes a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor is not provided in a package.

Claims (40)

1. A semiconductor device, comprising:

a substrate having a first side and a second side;

a epitaxial layer disposed over the second side;

a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and

a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor device is not provided in a package.

2. A semiconductor device as claimed in claim 1 , wherein the via and the bond pad are substantially coplanar.

3. A semiconductor device as claimed in claim 1 , wherein the substrate comprises one of: Si, SiGe, SiC or a III-V semiconductor material.

4. A semiconductor device as claimed in claim 1 , wherein the epitaxial layer comprises one of Si, SiGe, SiC or a III-V semiconductor material.

5. A semiconductor device as claimed in claim 1 , wherein the epitaxial layer is undoped, and the substrate is doped.

6. A semiconductor device as claimed in claim 5 , wherein a region beneath the bond pad is p-doped and the semiconductor device comprises a PIN diode.

7. A semiconductor device as claimed in claim 6 , wherein the substrate is n-doped.

8. An electronic device as claimed in claim 5 , wherein a region beneath the bond pad is p-doped and the semiconductor device comprises a PIN diode.

9. An electronic device as claimed in claim 8 , wherein the second substrate is n-doped.

10. A semiconductor device as claimed in claim 1 , further comprising an alignment fiducial disposed over the second side of the substrate.

11. A semiconductor device as claimed in claim 1 , comprising an alignment fiducial disposed over the second side of the substrate and substantially opposite the bond pad and another alignment fiducial disposed over the second side of the substrate and substantially opposite the conductive via.

12. An electronic device, comprising:

a first substrate comprising an electrical circuit; and

a semiconductor device, comprising:

a second substrate having a first side and a second side;

a epitaxial layer disposed over the second side;

a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and

a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor device is not provided in a package.

13. An electronic device as claimed in claim 12 , wherein the via and the bond pad are substantially coplanar.

14. An electronic device as claimed in claim 13 , comprising an alignment fiducial disposed over the second side of the second substrate and substantially opposite the bond pad and another alignment fiducial disposed over the second side of the second substrate and substantially opposite the conductive via.

15. An electronic device as claimed in claim 12 , wherein the second substrate comprises one of: Si, SiGe, SiC or a III-V semiconductor material.

16. An electronic device as claimed in claim 12 , wherein the epitaxial layer comprises one of Si, SiGe, SiC or a III-V semiconductor material.

17. An electronic device, as claimed in claim 12 , wherein the epitaxial layer is undoped, and the second substrate is doped.

18. An electronic device as claimed in claim 12 , further comprising an alignment fiducial disposed over the second side of the second substrate.

19. A semiconductor device, comprising:

a substrate having a first side and a second side;

a epitaxial layer disposed over the second side;

a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and

a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor device is not provided in a package, wherein both the epitaxial layer and the substrate are doped.

20. An electronic device, comprising:

a first substrate comprising an electrical circuit; and

a semiconductor device, comprising:

a second substrate having a first side and a second side;

a epitaxial layer disposed over the second side, wherein both the epitaxial layer and the second substrate are doped;

a conductive via extending through the epitaxial layer to the second side and comprising a conductive contact; and

a bond pad disposed over the epitaxial layer and comprising a conductive material, wherein the semiconductor device is not provided in a package.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded Feb 11, 2014
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 032239/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2008
From: LYPEN, WILLIAM J.; SNYDER, RICK D.
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 021220/0967 →