IP Library Granted Patent US 7,768,076
Granted Patent B2
US 7,768,076 · App. 12/113,290 · Granted Aug 3, 2010

Semiconductor device comprising an n-channel and p-channel MISFET

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,768,076
App. No.
12/113,290
Granted
Aug 3, 2010
Kind
B2
Abstract

A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×10 19 cm −3 in a portion adjacent an interface with the second metal layer.

Claims (11)

1. A semiconductor device comprising:

an n-channel MISFET comprising first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal film formed on the first gate insulating film, a first metal carbide film formed above the first metal film, and a first n-type polysilicon film formed on the first metal carbide film; and

a p-channel MISFET comprising second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal film formed on the second gate insulating film, a second metal carbide film formed above the second metal film, and a second n-type polysilicon film which is formed on the second metal carbide film and has a boron concentration of not more than 5×10 19 cm −3 in a portion adjacent to an interface with the second metal carbide film; and

the semiconductor device further comprising a third metal film between the second metal film and the second metal carbide film, wherein the first metal film and the third metal film contain the same metallic element.

2. The semiconductor device according to claim 1 , wherein the second n-type polysilicon film has a boron concentration of not more than 1×10 19 cm −3 in the portion adjacent the interface with the second metal layer carbide film.

3. The semiconductor device according to claim 1 , wherein the first metal film has a work function of not more than 4.3 eV, while the second metal film has a work function of not less than 4.8 eV.

4. The semiconductor device according to claim 1 , wherein the first and second gate insulating films each contain any one of oxides of Hf, Zr, Ti, Ta, Al, Sr, Y, and La.

5. A semiconductor device comprising:

an n-channel MISFET comprising first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal film formed on the first gate insulating film, a first metal carbide film formed above the first metal film, and a first n-type polysilicon film formed on the first metal carbide film; and

a p-channel MISFET comprising second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal film formed on the second gate insulating film, a second metal carbide film formed above the second metal film, and a second n-type polysilicon film which is formed on the second metal carbide film and has a boron concentration of not more than 5×10 19 cm −3 in a portion adjacent to an interface with the second metal carbide film; and

the semiconductor device further comprising a third metal film between the first metal film and the first metal carbide film, wherein the second metal film and the third metal film contain the same metallic element.

Assignments (7)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 028402 FRAME: 0733. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 24, 2014
From: EAST PENN MANUFACTURING CO.
To: WELLS FARGO BANK
Reel/Frame 033222/0390 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2012
From: EAST PENN MANUFACTURING CO.
To: WELLS FARGO BANK
Reel/Frame 028402/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2008
From: NAKAJIMA, KAZUAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 021099/0051 →
Priority Claims (1)
JP 2007-123362 · May 8, 2007 · national
Continuity (1)
Related Publication 20080277736A1 · Nov 13, 2008