IP Library Granted Patent US 7,709,360
Granted Patent B2
US 7,709,360 · App. 12/113,783 · Granted May 4, 2010

Method for manufacturing a crystalline silicon layer

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Quick Facts
Patent No.
US 7,709,360
App. No.
12/113,783
Granted
May 4, 2010
Kind
B2
Abstract

A method of forming a crystalline silicon layer on a microrough face of a substrate by reducing the microroughness of the face and then performing a metal induced crystallization process on the face is disclosed. The method further comprises, after metal induced crystallization and before removing the metal layer, removing silicon islands using the metal layer as a mask.

Claims (18)

1. A method for forming a crystalline silicon layer on a face of a substrate, wherein the face is microrough prior to forming the crystalline silicon layer, comprising:

reducing an amount of microroughness on a microrough face of a substrate, whereby a microflattened face is obtained;

performing a metal induced crystallization process on the microflattened face of the substrate by depositing a metal, oxidizing the metal, depositing silicon on the metal and annealing the metal and the silicon, whereby a crystalline silicon layer is obtained on the microflattened face and whereby a metal layer is obtained on the crystalline silicon layer, the metal layer comprising secondary crystallites and silicon islands;

removing the silicon islands, thereby using the metal layer as a mask; and

removing the metal layer.

2. The method of claim 1 , wherein removing the silicon islands comprises performing an etching step with an etching agent, wherein an etching speed of the etching agent for silicon and an etching speed of the etching agent for the metal are substantially the same.

3. The method of claim 1 , wherein removing the silicon islands comprises performing an etching step with an etching agent having a faster etching speed for silicon than for the metal.

4. The method of claim 1 , further comprising, before removing the silicon islands, performing an etching step for removing a metal oxide layer covering the silicon islands.

5. The method of claim 4 , wherein the etching step for removing the metal oxide layer comprises etching with an etchant comprising at least one of HF and H 3 PO 4 .

6. The method of claim 1 , further comprising, after removing the metal layer, a step of annealing at a temperature higher than 1000° C., whereby the surface of a seed layer comprising the secondary crystallites is smoothed.

7. The method of claim 6 , wherein the annealing step is performed in a hydrogen atmosphere.

8. The method of claim 1 , wherein the metal induced crystallization process comprises an aluminum induced crystallization process.

9. The method of claim 1 , wherein reducing the amount of microroughness comprises depositing a microflattening layer on the microrough face.

10. The method of claim 9 , wherein the microflattening layer is a dielectric layer.

11. The method of claim 1 , wherein the substrate comprises at least one material selected from the group consisting of a ceramic material, glass, a glass-ceramic material, mullite, alumina, and silicon nitride.

12. The method of claim 1 , further comprising:

epitaxially depositing a silicon layer on the crystalline silicon layer; and

constructing a solar cell from the substrate with the crystalline silicon layer and the epitaxially deposited silicon layer.

Assignments (2)
"IMEC" IS AN ALTERNATIVE OFFICIAL NAME FOR "INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW" Recorded Apr 7, 2010
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
To: IMEC
Reel/Frame 024200/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2008
From: VAN GESTEL, DRIES
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
Reel/Frame 021255/0885 →