Multi-lid semiconductor package
View Patent ↗A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.
1. A multi-lid semiconductor package comprising:
one or more die disposed on a substrate;
an interconnect disposed on the substrate;
one or more die lids;
a die thermal interface between the one or more die and the corresponding die lid or lids;
one or more substrate lids; and
a substrate interface between the substrate and the corresponding substrate lid or lids, wherein each of the one or more die lids is non-overlapping, in a plane view, with each of the one or more substrate lids.
2. The multi-lid semiconductor package of claim 1 , the multi-lid semiconductor package further comprising one or more discrete surface mount components disposed on the substrate.
3. The multi-lid semiconductor package of claim 1 , the multi-lid semiconductor package further comprising a sealant between the one or more die lids and the one or more substrate lids and the substrate.
4. The multi-lid semiconductor package of claim 1 , the multi-lid semiconductor package further comprising at least one of different lid materials or different thermal interface materials for die having different power dissipation, temperature, or reliability requirements.
5. The multi-lid semiconductor package of claim 1 , wherein the one or more die lids and the one or more substrate lids differ in at least one of construction, design, placement, or thermal performance.
6. The multi-lid semiconductor package of claim 1 , wherein the one or more die lids are placed selectively across the multi-lid semiconductor package relative to the one or more die.
7. The multi-lid semiconductor package of claim 1 , wherein a thickness of the die thermal interface is selectively controlled across the multi-lid semiconductor package.
8. The multi-lid semiconductor package of claim 1 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more die lids are different from each another.
9. The multi-lid semiconductor package of claim 1 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more substrate lids are different from each another.
10. The multi-lid semiconductor package of claim 1 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more die lids and the one or more substrate lids are different from each another.
11. A system comprising a multi-lid semiconductor package, the multi-lid semiconductor package comprising:
one or more die disposed on a substrate;
an interconnect disposed on the substrate;
one or more die lids;
a die thermal interface between the one or more die and the corresponding die lid or lids;
one or more substrate lids; and
a substrate interface between the substrate and the corresponding substrate lid or lids, wherein each of the one or more die lids is non-overlapping, in a plane view, with each of the one or more substrate lids.
12. The system of claim 11 , the multi-lid semiconductor package further comprising one or more discrete surface mount components disposed on the substrate.
13. The system of claim 11 , the multi-lid semiconductor package further comprising a sealant between the one or more die lids and the one or more substrate lids and the substrate.
14. The system of claim 11 , the multi-lid semiconductor package further comprising at least one of different lid materials or different thermal interface materials for die having different power dissipation, temperature, or reliability requirements.
15. The system of claim 11 , wherein the one or more die lids and the one or more substrate lids differ in at least one of construction, design, placement, or thermal performance.
16. The system of claim 11 , wherein the one or more die lids are placed selectively across the multi-lid semiconductor package relative to the one or more die.
17. The system of claim 11 , wherein a thickness of the die thermal interface is selectively controlled across the multi-lid semiconductor package.
18. The system of claim 11 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more die lids are different from each another.
19. The system of claim 11 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more substrate lids are different from each another.
20. The system of claim 11 , wherein a elevation (z-dimensional rise from the horizontal seating plane of the substrate) of the one or more die lids and the one or more substrate lids are different from each another.