Gate drive circuit, display substrate having the same, and method thereof
View Patent ↗A gate drive circuit includes a shift register, a clock wiring and a start wiring. The shift register includes a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals. The clock wiring is extended along the first direction. The clock wiring is electrically connected to a plurality of clock connecting wirings extended in a second direction crossing the first direction to deliver a clock signal to the stages. The start wiring includes the first wiring extended along the first direction and a second wiring connected to the first wiring and extended in the first direction to cross with the clock connecting wirings so as to deliver a vertical start signal to a first stage. Therefore, a structure of a signal wiring delivering a vertical start signal is changed, thereby protecting the gate drive circuit from static electricity.
1. A gate drive circuit comprising:
a shift register including a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals;
a clock wiring extended along the first direction, the clock wiring electrically connected to a plurality of clock connecting wirings extended in a second direction crossing the first direction to deliver a clock signal to the stages; and
a start wiring including a first wiring extended along the first direction and a second wiring connected to the first wiring and extended along the first direction to cross with the clock connecting wirings so as to deliver a vertical start signal to a first stage among the stages,
wherein capacitors are formed where the second wiring of the start wiring crosses the clock connecting wirings, and static electricity applied to the start wiring is dispersed through the capacitors to decrease energy of static electricity applied to the shift register.
2. The gate drive circuit of claim 1 , further comprising a power wiring extended along the first direction, the power wiring connected to a plurality of power connecting wirings extended along the second direction to deliver a power signal to the stages.
3. The gate drive circuit of claim 2 , wherein the second wiring of the start wiring crosses with the power connecting wirings and the clock connecting wirings.
4. The gate drive circuit of claim 2 , wherein the clock wiring is formed adjacent a first side of the power wiring, and the first wiring of the start wiring is formed adjacent a second side of the power wiring opposite to the first side of the power wiring, such that the power wiring is formed between the clock wiring and the first wiring of the start wiring.
5. The gate drive circuit of claim 4 , wherein the start wiring further comprises a third wiring extended from the second wiring to deliver the vertical start signal to a last stage among the stages, the third wiring crossing at least one of the clock connecting wirings and the power connecting wirings.
6. The gate drive circuit of claim 5 , wherein the second and third wirings are formed from a metal layer that is different from the clock connecting wirings and the power connecting wirings.
7. The gate drive circuit of claim 2 , wherein the first wiring is formed between the clock wiring and the power wiring to cross with at least one of the clock connecting wirings and the power connecting wirings.
8. The gate drive circuit of claim 7 , wherein the start wiring further comprises a third wiring extended from the second wiring to deliver the vertical start signal to a last stage among the stages, the third wiring crossing at least one of the clock connecting wirings and the power connecting wirings.
9. The gate drive circuit of claim 8 , wherein the first and second wirings are formed from a metal layer that is different from the clock connecting wirings and the power connecting wirings.
10. The gate drive circuit of claim 1 , wherein the clock wiring comprises:
a first clock wiring delivering a first clock signal to odd stages through the clock connecting wirings; and
a second clock wiring delivering a second clock signal having a phase opposite to the first clock signal to even stages through the clock connecting wirings.
11. The gate drive circuit of claim 1 , wherein the start wiring further comprises a third wiring extended from the second wiring to deliver the vertical start signal to a last stage among the stages, the third wiring crossing the clock connecting wirings.
12. A display substrate comprising:
a plurality of pixel parts formed in a display area of a base substrate, the pixel parts electrically connected to a plurality of data lines extended along a first direction and a plurality of gate lines extended along a second direction crossing the first direction; and
a gate drive circuit comprising:
a shift register formed in a peripheral area surrounding the display area, the shift register including a plurality of stages to output a plurality of gate signals;
a clock wiring electrically connected to a plurality of clock connecting wirings extended along the second direction to deliver a clock signal to the stages; and
a start wiring including a first wiring extended along the first direction and a second wiring connected to the first wiring and extended along the first direction to cross with the clock connecting wirings so as to deliver a vertical start signal to a first stage among the stages,
wherein capacitors are formed where the second wiring of the start wiring crosses the clock connecting wirings, and static electricity applied to the start wiring is dispersed through the capacitors to decrease energy of static electricity applied to the shift register.
13. The display substrate of claim 12 , further comprising a power wiring extended along the first direction, the power wiring connected to a plurality of power connecting wirings extended along the second direction to deliver a power signal to the stages.
14. The display substrate of claim 13 , wherein the clock wiring is formed adjacent a first side of the power wiring, a first wiring of the start wiring formed adjacent a second side of the power wiring opposite to the first side of the power wiring, such that the power wiring is formed between the clock wiring and the first wiring of the start wiring.
15. The display substrate of claim 14 , wherein the start wiring further comprises a third wiring extended from the second wiring to deliver the vertical start signal to a last stage among the stages, the third wiring crossing at least one of the clock connecting wirings and the power connecting wirings.
16. The display substrate of claim 15 , wherein the second and third wirings are formed from a metal layer that is different from the clock connecting wirings and the power connecting wirings.
17. The display substrate of claim 13 , wherein the first wiring is formed between the clock wiring and the power wiring to cross with at least one of the clock connecting wirings and the power connecting wirings.
18. The display substrate of claim 17 , wherein the start wiring further comprises a third wiring extended from the second wiring to deliver the vertical start signal to a last stage among the stages, the third wiring crossing at least one of the clock connecting wirings and the power connecting wirings.
19. The display substrate of claim 18 , wherein the first and second wirings are formed from a metal layer that is different from the clock connecting wirings and the power connecting wirings.
20. The display substrate of claim 12 , wherein the clock wiring comprises:
a first clock wiring delivering a first clock signal to odd stages through the clock connecting wirings; and
a second clock wiring delivering a second clock signal having a phase opposite to the first clock signal to even stages through the clock connecting wirings.
21. A method of enhancing a driving reliability of a gate drive circuit, the gate drive circuit including a shift register including a plurality of stages arranged in a first direction on a base substrate to output a plurality of gate signals, and a clock wiring extended along the first direction, the clock wiring electrically connected to a plurality of clock connecting wirings extended in a second direction crossing the first direction to deliver a clock signal to the stages, the method comprising:
providing a start wiring to deliver a vertical start signal to a first stage among the stages, the start wiring including a first wiring extended along the first direction and a second wiring connected to the first wiring and extended along the first direction; and
crossing the second wiring of the start wiring with the clock connecting wirings;
wherein capacitors are formed where the second wiring crosses the clock connecting wirings, and static electricity applied to the start wiring is dispersed through the capacitors to decrease energy of static electricity applied to the shift register.