Semiconductor device package with internal device protection
View Patent ↗An integral impedence is formed on or within a lead frame pin of a semiconductor package and receives a connection from an electrode of a semiconductor die within the package to eliminate the need for adjustment and protective impedences external of the package. The impedence comprises passives such as resistors, capacitors, diodes or inductors which modify the performance of the package for new semiconductor device characteristics. The impedences may have positive or negative temperature coefficients and are in close thermal communication with the semiconductor die.
1. A semiconductor package comprising a semiconductor chip; a flat conductive support for receiving on side of said semiconductor chip; at least one electrode in the opposite side of said chip; at least one elongated lead which is generally coplanar with said flat conductive support; an impedance element fixed on top of said elongated lead for adjusting for a characteristic of said semiconductor chip; and a connector having one end connected to said at least one electrode and its opposite end connected in series with said impedance element and said elongated lead, wherein said connector is connected without bond-wires.
2. The semiconductor package of claim 1 , wherein said semiconductor chip is an IC having a plurality of electrodes on its said opposite side.
3. The semiconductor package of claim 1 , wherein said semiconductor chip is a power electronics switching device.
4. The semiconductor package of claim 1 , which further includes a plastic housing enclosing said semiconductor chip, said connector and said impedance element; an end portion of said at least one elongated lead and a portion of said flat conductor support extending through the surface of said plastic housing to be accessible for connection to external circuits.
5. The semiconductor package of claim 1 , wherein said flat conductor support and said at least one elongated lead are elements of a common lead frame.
6. The semiconductor package of claim 1 , wherein said opposite end of said connector is connected directly to said impedance element.
7. The semiconductor package of claim 1 , wherein said opposite end of said connector is connected directly to said elongated lead.
8. The semiconductor package of claim 1 , wherein said impedance element is a resistor plated onto a surface of said elongated lead.
9. The semiconductor package of claim 8 , wherein said opposite end of said connector is connected directly to said impedance element.
10. The semiconductor package of claim 1 , wherein said impedance element is a resistor formed within the body of the length of said elongated lead.
11. The semiconductor package of claim 10 , wherein said opposite end of said connector is connected directly to said elongated lead.
12. The semiconductor package of claim 1 , wherein said impedance element comprises a capacitor fixed atop a portion of the surface of said elongated lead.
13. The semiconductor package of claim 1 , wherein said semiconductor chip has a second electrode on its said opposite side and a current sense lead extending from and connecting said second electrode to said elongated lead and by passing said impedance element.
14. The semiconductor package of claim 6 , wherein said semiconductor chip has a second electrode on its said opposite side and a current sense lead extending from and connecting said second electrode to said elongated lead and by-passing said impedance element.
15. The semiconductor package of claim 12 , wherein said semiconductor chip has a second electrode on its said opposite side and a current sense lead extending from and connecting said second electrode to said elongated lead and by-passing said impedance element.
16. The semiconductor package of claim 8 , wherein said resistor has a predetermined intentional thermal coefficient of resistance.
17. The semiconductor package of claim 10 , wherein said resistor has a predetermined intentional thermal coefficient of resistance.