Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter
A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
1. A proximity-to-optical memory module, comprising:
a substrate;
at least one optical channel;
an interface chip disposed on the substrate and coupled to the optical channel through an electrical-to-optical and optical-to electrical converter and further including proximity communication transmitting and receiving elements incorporated therein; and
a plurality of memory chips disposed on the substrate and each including proximity communication transmitting and receiving elements incorporated therein and electrically coupled to proximity communication transmitting and receiving elements of the interface chip to form proximity communication channels.
2. The memory module of claim 1 , wherein the proximity communication transmitting and receiving elements comprise metal pads which form respective capacitors when coupled to the pads of an adjacent chip.
3. The memory module of claim 1 , wherein the interface chip further comprises an electronic input buffer and an electronic output buffer buffering data between the at least one optical channel and the memory chips.
4. The memory module of claim 1 ,
wherein the interface chip and the memory chips have upwardly facing metal pads, and
further comprising bridge chips having downwardly facing metal pads and sitting atop the interface and memory chips to form proximity communication channels between them.
5. The memory module of claim 1 , wherein a plurality of memory chips are arranged in a linear array and wherein proximity communication channels are formed between neighboring ones of the memory chips.
6. The memory module of claim 5 ,
wherein the interface chip and the memory chips have upwardly facing metal pads, and
further comprising bridge chips having downwardly facing metal pads and sitting atop the interface and memory chips to form proximity communication channels between them.
7. The memory module of claim 1 , wherein a plurality of memory chips are arranged in a two-dimensional array around the interface chip.
8. The memory module of claim 7 , wherein at least some of the memory chips are coupled by proximity communication channels to four neighboring memory chips.
9. The memory module of claim 7 , wherein four memory chips are coupled to respective sides of the interface chip through at least four respective proximity communication channels.
10. The memory module of claim 7 , including a second interface chip surrounded by a plurality of the memory chips in the two-dimensional array, wherein all the memory chips and the two interface chips are interconnected by a proximity communication network.
11. The memory module of claim 1 , wherein a plurality of the memory chips are disposed adjacent to each of a plurality of sides of the interface chip and connected to it through respective proximity communication channels.
12. The memory module of claim 1 , wherein the memory chips have a narrow side and a wide side larger than the narrow side and wherein the plurality of the memory chips have their narrow sides disposed adjacent to the sides of the interface chip to form proximity communication channels along the narrow side.
13. A proximity-to-optical memory module, comprising:
a substrate;
an interface chip disposed on the substrate and including
optical couplers for coupling to at least two optical channels;
an optical-to-electrical converter coupled to one of the optical couplers,
an electrical-to-optical converter coupled to another of the optical couplers,
an input buffer electrically coupled to the optical-to-electrical converter,
an output buffer electrically coupled to the electrical-to-optical converter,
a set of first pads connected to the input buffer, and
a set of second pads connected to the output buffer; and
at least one memory chip each comprising
a plurality of memory locations,
a plurality of first pads connected on input paths to the memory locations, and
a plurality of second pads connected on output paths from the memory locations;
wherein, when principal surfaces of the memory chip and the interface chip are juxtaposed, the juxtaposed first memory pads are configured to form capacitively coupled links between the interface chip and the memory chip and the juxtaposed second memory pads are configured to form capacitively coupled links between the interface chip and the memory chip.
14. A proximity-to-optical memory module, comprising:
a substrate;
an interface chip disposed on the substrate and including
optical couplers for coupling to at least two optical fibers;
an optical-to-electrical converter coupled to one of the optical couplers,
an electrical-to-optical converter coupled to another of the optical couplers,
an input buffer electrically coupled to the optical-to-electrical converter,
an output buffer electrically coupled to the electrical-to-optical converter,
a set of first pads connected to the input buffer, and
a set of second pads connected to the output buffer;
at least one memory chip disposed on the substrate and each comprising
a plurality of memory locations,
a plurality of third pads connected on input paths to the memory locations, and
a plurality of fourth pads connected on output paths to the memory locations; and
at least one bridge chip disposed on both the interface chip and the memory chip on sides thereof opposite the substrate and including
a plurality of fifth pads in corresponding opposition to the first pads and forming capacitively coupled links therebetween,
a plurality of sixth pads in corresponding opposition to the second pads and forming capacitively coupled links therebetween,
a plurality of seventh pads in corresponding opposition to the third pads and forming capacitively coupled links therebetween,
a plurality of eighth pads in corresponding opposition to the fourth pads and forming capacitively coupled links therebetween, and
signal channels linking corresponding ones of the fifth and seventh pads and corresponding ones of the sixth and eighth pads, whereby the interface chip and the memory chip are in communication through the bridge chip.