Enhancement mode III-nitride FET
View Patent ↗A III-nitride switch includes a recessed gate contact to produce a nominally off, or an enhancement mode, device. By providing a recessed gate contact, a conduction channel formed at the interface of two III-nitride materials is interrupted when the gate electrode is inactive to prevent current flow in the device. The gate electrode can be a schottky contact or an insulated metal contact. Two gate electrodes can be provided to form a bi-directional switch with nominally off characteristics. The recesses formed with the gate electrode can have sloped sides. The gate electrodes can be formed in a number of geometries in conjunction with current carrying electrodes of the device.
1. A method of fabricating a semiconductor device, comprising:
forming a III-nitride heterojunction over a substrate, said III-nitride heterojunction having a two-dimensional electron gas at an interface of a first III-nitride layer and a second III-nitride layer;
forming a recess to obtain an altered region in said two-dimensional electron gas;
forming a gate over said altered region, said gate situated over said first III-nitride layer and said second III-nitride layer, said gate completely filling said recess and disposed on a top surface of said second III-nitride layer;
forming ohmic contacts directly on said top surface of said second III-nitride layer.
2. The method of claim 1 , wherein said altered region interrupts said two-dimensional electron gas.
3. The method of claim 1 , wherein said recess is formed in said second III-nitride layer.
4. The method of claim 1 , wherein said recess includes tapering sidewalls.
5. The method of claim 1 , wherein said gate is schottky coupled to said second III-nitride layer.
6. The method of claim 1 , wherein said first III-nitride layer is comprised of GaN and said second III-nitride layer is comprised of AlGaN.
7. The method of claim 1 , wherein said semiconductor device comprises an enhancement mode device.
8. The method of claim 1 , wherein forming said recess comprises forming an etched back region of said second III-nitride layer.
9. The method of claim 1 , wherein said gate is formed in said recess.
10. A method of fabricating a semiconductor device, comprising:
forming a III-nitride heterojunction over a substrate, said III-nitride heterojunction having a two-dimensional electron gas at an interface of a first III-nitride layer and a second III-nitride layer;
forming a recessed gate in said second III-nitride layer to obtain an altered region in said two-dimensional electron gas, said recessed gate situated over said first III-nitride layer and said second III-nitride layer, and said recessed gate completely filling a recess in said second III-nitride layer and disposed on a top surface of said second III-nitride layer;
forming ohmic contacts directly on said top surface of said second III-nitride layer.
11. The method of claim 10 , wherein said altered region interrupts said two-dimensional electron gas.
12. The method of claim 10 , wherein said recessed gate includes tapering sidewalls.
13. The method of claim 10 , wherein said recessed gate is formed in an etched back region of said second III-nitride layer.
14. The method of claim 10 , wherein said recessed gate is schottky coupled to said second III-nitride layer.
15. The method of claim 10 , wherein said semiconductor device comprises an enhancement mode device.
16. The method of claim 10 , wherein said first III-nitride layer is comprised of GaN and said second III-nitride layer is comprised of AlGaN.