SYSTEM AND METHOD FOR F-SCCH AND R-ODCCH PERFORMANCE IMPROVEMENT
A control channel encoder, e.g., in a UMB system, uses a channel structure that can efficiently transmit more information bits, yet achieve sufficient detection and false alarm performance. A control channel encoder can use a fixed encoder packet size, tail-biting convolutional coding, and Cyclical Redundancy Check (CRC). A control channel decoder can use a circular Viterbi decoding algorithm and a circular trellis check.
1 . A channel encoder configured to encode M data bits onto a channel for further modulation, comprising:
a first cyclical redundancy check (CRC) encoding block configured to receive the M data bits, generate L CRC bits, and add the L CRC bits to the M data bits;
a tail-biting convolutional encoder coupled to the first CRC encoding block, the tail-biting convolutional encoder configured to encode the M+L bits using a tail biting technique with a constraint length K=8 and generate output symbols; and
a sequence repetition block coupled to the tail-biting convolutional encoder, the sequence repetition block configured to add a repetition sequence to the output symbols.
2 . The channel encoder of claim 1 , further comprising a modulator coupled to the sequence repletion block, the modulator configured to modulate the output symbols.
3 . The channel encoder of claim 1 , wherein the channel is selected from at least one of the following:
the Forward Share Control Channel (F-SCCH); and
Reverse OFDM Dedicated Control Channel (R-ODCCH).
4 . The channel encoder of claim 3 , wherein M is 25 bits and L is 15 bits if the channel is the F-SCCH, and wherein M is 15 bits and L is 15 bits if the channel is the R-ODCCH.
5 . The channel encoder of claim 2 , wherein the modulator is further configured to modulate the output symbols using QPSK (Quadrature Phase Shift Keying).
6 . The channel encoder of claim 1 , further comprising an interleaver coupled between the (CRC) encoding block and the tail-biting convolutional encoder.
7 . A method for encoding information bits onto a control channel for further modulating, comprising:
receiving an M-bit payload;
generating L-CRC bits of the received M-bit payload data bits;
adding the L-CRC bits to the payload data bits;
generating output symbols from the L-CRC and payload data bits using a tail biting technique with a constraint length of K=8; and
performing repetition sequencing on the output symbols.
8 . The method of encoding information of claim 7 , further comprising modulating the output symbols after performing the repetition sequencing.
9 . The method of encoding information of claim 7 , wherein the channel is selected from at least one of the following:
the Forward Share Control Channel (F-SCCH); and
Reverse OFDM Dedicated Control Channel (R-ODCCH).
10 . The method of encoding information of claim 10 , wherein M is 25 bits and L is 15 bits if the channel is the F-SCCH, and wherein M is 15 bits and L is 15 bits if the channel is the R-ODCCH.
11 . The method of claim 8 , wherein modulating the output symbols is using QPSK.
12 . A channel decoder configured to decode output symbols received from a control channel comprising:
a sequence derepetition block configured to remove repetition sequence from the demodulated output symbols;
a tail-biting convolutional decoder coupled with the deinterleaving block, the tail-biting convolutional decoder configured to decode the output symbols using a constraint length K=8 and generate data bits;
a first cyclical redundancy check (CRC) decoding block coupled to the tail-biting convolutional decoder, the first CRC decoding block configured to check the data bits and produce payload data bits.
13 . The channel decoder of claim 12 , further comprising a demodulator, coupled to the input of the sequence derepetition block, the demodulator configured to demodulate the output symbols received from a control channel.
14 . The channel decoder of claim 12 , wherein the tail biting convolutional decoder is configured to decode the output symbols using circular Viterbi decoding algorithm and a circular trellis check.
15 . The channel encoder of claim 14 , wherein the trellis starts in at least one of the following conditions:
all states with the same state metric; and
all states from a fixed (zero) state.
16 . The channel encoder of claim 12 , wherein the channel is selected from at least one of the following:
the Forward Share Control Channel (F-SCCH); and
Reverse OFDM Dedicated Control Channel (R-ODCCH).
17 . The channel encoder of claim 13 , wherein the demodulator configured to modulate the output symbols using QPSK.
18 . A method for decoding demodulated output symbols on a control channel, comprising:
receiving the output symbols from a control channel;
removing a repetition sequence from the demodulated output symbols;
decoding the output symbols using tail-biting convolutional decoding with a constraint length K=8 and generating data bits; and
performing a first cyclical redundancy check (CRC) on the data bits.
19 . The method for decoding of claim 18 , further including demodulating the output symbols after receiving the output symbols and before decoding the output symbols using tail-biting convolutional decoding.
20 . The method for decoding of claim 18 , wherein the tail biting convolutional decoder is configured to decode the output symbols using circular Viterbi decoding algorithm and a circular trellis check.
21 . The method for decoding of claim 19 , wherein the trellis starts in at least one of the following conditions:
all states with the same state metric; and
all states from a fixed (zero) state.
22 . The method for decoding of claim 18 , wherein the channel is selected from at least one of the following:
the Forward Share Control Channel (F-SCCH); and
the Reverse OFDM Dedicated Control Channel (R-ODCCH).
23 . The method for decoding of claim 18 , wherein the demodulating is using QPSK.