Calibrated quadrature generation for multi-GHz receiver
View Patent ↗An integrated receiver circuit includes a phase locked loop circuit ( 21 ) with a voltage controlled oscillator (VCO) ( 25 ) and a quadrature generator circuit ( 29 ) which uses hybrid-branch line coupler circuits ( 27, 28 ) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits ( 27, 28 ) are tuned by same control voltage ( 25 a ) that controls the VCO ( 25 ). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit ( 27, 28 ) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit ( 21 ).
1. A receiver circuit, comprising:
a phase lock loop (PLL) circuit coupled to receive a reference signal, said phase lock loop circuit comprising a voltage controlled oscillator circuit that is controlled by a control voltage to generate a first PLL output signal and a second PLL output signal; and
a quadrature generator circuit comprising:
a first hybrid branch line coupler circuit that is coupled to receive the first PLL output signal and that is controlled by the control voltage to generate first and second local oscillator signals separated in phase from each other by substantially ninety degrees, and
a second hybrid branch line coupler circuit that is coupled to receive the second PLL output signal and that is controlled by the control voltage to generate third and fourth local oscillator signals separated in phase from each other by substantially ninety degrees.
2. The receiver circuit of claim 1 , where the phase lock loop circuit comprises:
a phase detector having a first input coupled to receive the reference signal;
a low pass filter coupled to an output of the phase detector for generating the control voltage;
a differential single-inductor voltage controlled oscillator coupled to an output of the low pass filter for generating the first PLL output signal and the second PLL output signal under control of the control voltage; and
a frequency dividing circuit having an input coupled to the second PLL output signal of the differential single-inductor voltage controlled oscillator and an output coupled to a second input of the phase detector.
3. The receiver circuit of claim 2 where the differential single-inductor voltage controlled oscillator comprises a parallel resonance LC tank circuit in which a first inductor L 1 , a constant capacitor C 1 , and a variable capacitor C 2 are connected in parallel.
4. The receiver circuit of claim 3 , where the first hybrid branch line coupler circuit comprises:
a first node coupled to a reference voltage through a first variable capacitor;
a second node coupled to the reference voltage through a second variable capacitor;
a third node coupled to the reference voltage through a third variable capacitor;
a fourth node coupled to the reference voltage through a fourth variable capacitor;
a first branch comprising a second inductor L 2 coupled between the first and second nodes;
a second branch comprising a third inductor L 3 coupled between the third and fourth nodes;
a third branch comprising a first constant capacitor coupled between the first and third nodes; and
a fourth branch comprising a second constant capacitor coupled between the second and fourth nodes;
where the first inductor L 1 , second inductor L 2 , and third inductor L 3 each have substantially the same inductance value; where the constant capacitor C 1 , first constant capacitor, and second constant capacitor each have substantially the same capacitance value; and where the variable capacitor C 2 , first variable capacitor, second variable capacitor, third variable capacitor and fourth variable capacitor each have substantially the same capacitance value that is controlled by the control voltage.
5. The receiver circuit of claim 4 , where the second hybrid branch line coupler circuit comprises:
a fifth node coupled to the reference voltage through a fifth variable capacitor;
a sixth node coupled to the reference voltage through a sixth variable capacitor;
a seventh node coupled to the reference voltage through a seventh variable capacitor;
an eighth node coupled to the reference voltage through an eighth variable capacitor;
a fifth branch comprising a fourth inductor L 4 coupled between the fifth and sixth;
a sixth branch comprising a fifth inductor L 5 coupled between the seventh and eighth nodes;
a seventh branch comprising a third constant capacitor coupled between the fifth and seventh nodes; and
an eighth branch comprising a fourth constant capacitor coupled between the sixth and eighth nodes;
where the first inductor L 1 , fourth inductor L 4 , and fifth inductor L 5 each have substantially the same inductance value; where the constant capacitor C 1 , third constant capacitor, and fourth constant capacitor each have substantially the same capacitance value; and where the variable capacitor C 2 , fifth variable capacitor, sixth variable capacitor, seventh variable capacitor and eighth variable capacitor each have substantially the same capacitance value that is controlled by the control voltage.
6. The receiver circuit of claim 2 where the differential single-inductor voltage controlled oscillator comprises:
a parallel resonance LC tank circuit in which a first inductor L 1 , a constant capacitor C 1 , and a variable capacitor C 2 are connected in parallel between first and second output nodes;
a first pair of cross-coupled transistors coupled between a first predetermined reference voltage and the first and second output nodes; and
a second pair of cross-coupled transistors coupled between a biasing transistor and the first and second output nodes.
7. The receiver circuit of claim 6 , where the first hybrid branch line coupler circuit comprises:
a first node coupled to a reference voltage through a first variable capacitor;
a second node coupled to the reference voltage through a second variable capacitor;
a third node coupled to the reference voltage through a third variable capacitor;
a fourth node coupled to the reference voltage through a fourth variable capacitor;
a first branch comprising a second inductor L 2 coupled between the first and second nodes;
a second branch comprising a third inductor L 3 coupled between the third and fourth nodes;
a third branch comprising a first constant capacitor coupled between the first and third nodes;
a fourth branch comprising a second constant capacitor coupled between the second and fourth nodes;
a third pair of cross-coupled transistors coupled between a first predetermined reference voltage and the first and second nodes; and
a fourth pair of cross-coupled transistors coupled between a biasing transistor and the first and second nodes;
where the first inductor L 1 , second inductor L 2 , and third inductor L 3 each have substantially the same inductance value; where the constant capacitor C 1 , first constant capacitor, and second constant capacitor each have substantially the same capacitance value; and where the variable capacitor C 2 , first variable capacitor, second variable capacitor, third variable capacitor and fourth variable capacitor each have substantially the same capacitance value that is controlled by the control voltage.
8. The receiver circuit of claim 7 , where the second hybrid branch line coupler circuit comprises:
a fifth node coupled to the reference voltage through a fifth variable capacitor;
a sixth node coupled to the reference voltage through a sixth variable capacitor;
a seventh node coupled to the reference voltage through a seventh variable capacitor;
an eighth node coupled to the reference voltage through an eighth variable capacitor;
a fifth branch comprising a fourth inductor L 4 coupled between the fifth and sixth;
a sixth branch comprising a fifth inductor L 5 coupled between the seventh and eighth nodes;
a seventh branch comprising a third constant capacitor coupled between the fifth and seventh nodes;
an eighth branch comprising a fourth constant capacitor coupled between the sixth and eighth nodes;
a third pair of cross-coupled transistors coupled between a first predetermined reference voltage and the third and fourth nodes; and
a fourth pair of cross-coupled transistors coupled between a biasing transistor and the third and fourth nodes;
where the first inductor L 1 , fourth inductor L 4 , and fifth inductor L 5 each have substantially the same inductance value; where the constant capacitor C 1 , third constant capacitor, and fourth constant capacitor each have substantially the same capacitance value; and where the variable capacitor C 2 , fifth variable capacitor, sixth variable capacitor, seventh variable capacitor and eighth variable capacitor each have substantially the same capacitance value that is controlled by the control voltage.
9. A method for generating quadrature local oscillator signals, comprising:
generating an analog control signal and first and second differential output signals from a phase lock loop circuit comprising a voltage controlled oscillator (VCO) core circuit;
applying the first and second differential output signals to first and second hybrid branch line coupler circuits, respectively, to generate calibrated quadrature local oscillator signals, where each of the first and second hybrid branch line coupler circuits comprises circuitry that replicates the VCO core circuit, and where each of the first and second hybrid branch line coupler circuits is controlled by the analog control signal to generate first and second local oscillator signals separated in phase from each other by substantially ninety degrees.
10. The method of claim 9 , further comprising applying the analog control signal to control the VCO core circuit, the first hybrid branch line coupler circuit, and the second hybrid branch line circuit, where the first hybrid branch line circuit is coupled to receive a first differential output signal from the phase lock loop circuit, and where the second hybrid branch line circuit is coupled to receive a second differential output signal from the phase lock loop circuit.
11. The method of claim 9 , where generating the analog control signal and the first and second differential output signals from a phase lock loop circuit comprises:
generating the analog control signal from an input reference clock signal with the phase lock loop circuit;
generating first and second differential output signals with the VCO core circuit under control of the analog control signal;
connecting the first and second differential output signals in feedback to the phase lock loop circuit.
12. The method of claim 11 , where generating the analog control signal comprises:
receiving the input reference clock signal;
comparing the input reference clock signal with a feedback signal provided by a frequency divider coupled to receive the first and second differential output signals, thereby generating an output signal corresponding to a phase difference between the input reference clock signal and the feedback signal; and
generating the analog control signal by filtering the output signal.
13. The method of claim 11 , where connecting the first and second differential output signals in feedback to the phase lock loop circuit comprises dividing the frequency of the first and second differential output signals.
14. The method of claim 11 , where generating first and second differential phase locked output signals comprises generating first and second differential phase locked output signals that are phase locked with the input reference clock signal.
15. The method of claim 9 , where applying the first and second differential output signals to first and second hybrid branch line coupler circuits comprises:
applying the first differential output signal to the first hybrid branch line coupler circuit that is controlled by the analog control signal to generate first and second local oscillator signals separated in phase from each other by substantially ninety degrees; and
applying the second differential output signal to the second hybrid branch line coupler circuit that is controlled by the analog control signal to generate third and fourth local oscillator signals separated in phase from each other by substantially ninety degrees.
16. The method of claim 9 , where applying the first and second differential output signals to first and second hybrid branch line coupler circuits comprises:
applying the first and second differential output signals to first and second hybrid branch line coupler circuits, respectively, to generate calibrated quadrature local oscillator signals, where each of the first and second hybrid branch line coupler circuits comprises an inductor, a variable capacitor, and a pair of cross-coupled transistors coupled in parallel.
17. A calibrated quadrature generator circuit, comprising:
a phase lock loop circuit coupled to receive a reference signal, said phase lock loop circuit comprising a voltage controlled oscillator core circuit that is controlled by a control voltage to generate first and second differential output signals;
a first hybrid branch line coupler circuit comprising a first replica of the voltage controlled oscillator core circuit that is coupled to receive the first differential output signal and that is controlled by the control voltage to generate first and second local oscillator signals separated in phase from each other by substantially ninety degrees, and
a second hybrid branch line coupler circuit comprising a second replica of the voltage controlled oscillator core circuit that is coupled to receive the second differential output signal and that is controlled by the control voltage to generate third and fourth local oscillator signals separated in phase from each other by substantially ninety degrees.
18. The calibrated quadrature generator circuit of claim 17 , where the voltage controlled oscillator core circuit comprises an inductor and a variable capacitor coupled in parallel.
19. The calibrated quadrature generator circuit of claim 17 , where the voltage controlled oscillator core circuit comprises an inductor, a variable capacitor, and a pair of cross-coupled transistors coupled in parallel.
20. The calibrated quadrature generator circuit of claim 18 , where the variable capacitor comprises two variable capacitors coupled in series to a common node.