Periodic and conditional execution of DMA operations

1. A method of scheduling Direct Memory Access (DMA) operations in a NAND memory environment, the method comprising:

providing blocks in a first DMA chain, each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer of the pair of pointers pointing to a command structure to be executed or a data structure to be moved, a second pointer of the pair of pointers pointing to a next block in the first DMA chain;

using a DMA engine to process successive operations in the first DMA chain, wherein the DMA engine tracks whether a conditional operation has already been executed by checking a consumption semaphore included in the corresponding conditional block;

tracking time remaining in an interval for processing the first DMA chain;

maintaining a second DMA chain of conditional blocks, each conditional block corresponding to a conditional operation and containing an estimate of time needed to complete processing the conditional operation; and

executing a given conditional operation from the second DMA chain if the remaining time in the interval for processing the first DMA chain is greater than the estimated time to complete processing of the given conditional operation.

2. The method according to claim 1 , wherein a last block in the first DMA chain points to the second DMA chain.

3. The method according to claim 1 , wherein each block in the first DMA chain and the second DMA chain includes an exclusion semaphore for preventing the DMA engine from executing an operation associated with the block.

4. The method according to claim 3 , wherein if the DMA engine is prevented from executing an operation associated with a given block, the DMA engine repeatedly attempts to fetch the given block until the given block is reset.

5. The method according to claim 3 , wherein if the DMA engine is prevented from executing an operation associated with a given block, the DMA monitors a bus for any write to a location of the given block, and attempts to refetch the given block if such a write is detected.

6. The method according to claim 1 , wherein a length of the interval is set based on an application being executed.

7. The method according to claim 1 , wherein upon expiration of the interval, the DMA engine begins processing a next scheduled DMA chain.

8. The method according to claim 1 , wherein a system processor monitors the second DMA chain and reclaims executed blocks of the second DMA chain in order to supply conditional pointers to new conditional blocks.

9. An apparatus for scheduling Direct Memory Access (DMA) operations in a NAND memory environment, the apparatus comprising:

a block providing unit configured to provide blocks in a first DMA chain, each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a first pointer of the pair of pointers pointing to a command structure to be executed or a data structure to be moved, a second of the pair of pointers pointing to a next block in the first DMA chain;

a DMA engine configured to process successive operations in the first DMA chain, wherein the DMA engine tracks whether a conditional operation has already been executed by checking a consumption semaphore included in the corresponding conditional block;

a period counter configured to track time remaining in an interval for processing the first DMA chain,

wherein conditional operations are maintained in a second DMA chain of conditional blocks, each conditional block corresponding to a conditional operation and containing an estimate of the time needed to complete processing the conditional operation; and

wherein the DMA engine executes a given conditional operation from the second DMA chain if the remaining time in the interval for processing the first DMA chain is greater than the estimated time to complete processing of the given conditional operation.

10. The apparatus according to claim 9 , wherein a last block in the first DMA chain points to the second DMA chain.

11. The apparatus according to claim 9 , wherein each block in the first DMA chain and the second DMA chain includes an exclusion semaphore for preventing the DMA engine from executing an operation associated with the block.

12. The apparatus according to claim 11 , wherein if the DMA engine is prevented from executing an operation associated with a given block, the DMA engine repeatedly attempts to fetch the given block until the given block is reset.

13. The apparatus according to claim 11 , wherein if the DMA engine is prevented from executing an operation associated with a given block, the DMA monitors a bus for any write to a location of the given block, and attempts to refetch the given block if such a write is detected.

14. The apparatus according to claim 9 , wherein the period counter sets the length of the interval based on an application being executed.

15. The apparatus according to claim 9 , wherein upon the expiration of the interval, the DMA engine begins processing a next scheduled DMA chain.

16. The apparatus according to claim 9 , wherein a system processor monitors the second DMA chain and reclaims executed command blocks of the second DMA chain in order to supply conditional pointers to new conditional blocks.