Area efficient first-in first-out circuit
View Patent ↗A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner, and provides the data to the read port. The control logic also disables power to selected ones of the X memories when they are not being written to or read from. The FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.
1. A FIFO memory having an available capacity of no more than N words deep by M bits wide, comprising:
a write port for receiving data to store in the FIFO memory,
a read port for providing the data stored in the FIFO memory,
X memories to store the data, where each of the X memories has a size of N/X by M, and
control logic for receiving the data from the write port, writing the data into at least one of the X memories in a serial write manner, reading the data from at least one of the X memories in a serial read manner, and providing the data to the read port, the control logic also for disabling power to selected ones of the X memories when they are not being written to or read from,
where the FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.
2. The FIFO memory of claim 1 , wherein the X memories are individually configured as one of 211 and 222 memories.
3. The FIFO memory of claim 1 , wherein the X memories are all configured as one of 211 and 222 memories.
4. An integrated circuit including the FIFO memory of claim 1 .
5. A FIFO memory having an available capacity of no more than N words deep by M bits wide, comprising:
a write port for receiving data to store in the FIFO memory,
a read port for providing the data stored in the FIFO memory,
X memories to store the data, where each of the X memories has a size of N/(X−1) by M, and
control logic for receiving the data from the write port, writing the data into at least one of the X memories in a serial write manner, reading the data from at least one of the X memories in a serial read manner, and providing the data to the read port,
where the FIFO memory is configured to only one of read and write the data at a given time to a given one of the X memories.
6. The FIFO memory of claim 5 , wherein the X memories are all configured as 111 memories.
7. The FIFO memory of claim 5 , wherein the control logic is also for disabling power to selected ones of the X memories when they are not being written to or read from.
8. An integrated circuit including the FIFO memory of claim 5 .
9. A FIFO memory having an available capacity of no more than N words deep by M bits wide, comprising:
a write port for receiving data to store in the FIFO memory,
a read port for providing the data stored in the FIFO memory,
X memories to store the data, where each of the X memories has a size of N/(X−1) by M,
one additional memory having a size of N/(X−1) by M, and
control logic for receiving the data from the write port, writing the data into at least one of the X memories in a serial write manner, reading the data from at least one of the X memories in a serial read manner, and providing the data to the read port,
where the FIFO memory is configured to only one of read and write the data at a given time to a given one of the X memories, simultaneously write the data to a given one of the X memories and the one additional memory, and selectively read the data from only one of either the X memories or the one additional memory at a given time.
10. The FIFO memory of claim 9 , wherein the X memories are all configured as 111 memories.
11. The FIFO memory of claim 9 , wherein the one additional memory is configured as a 222 memory.
12. The FIFO memory of claim 9 , wherein the control logic is also for disabling power to selected ones of the X memories when they are not being written to or read from.
13. An integrated circuit including the FIFO memory of claim 9 .