Mitigating fractional spurs in fractional-N frequency synthesizer systems

1. A fractional-N frequency synthesizer circuit, the frequency synthesizer circuit comprising:

a closed-loop feedback control system configured to generate an oscillating output signal defined by a divider count;

a modulator circuit configured to generate a sequence of divider counts; and

a selection circuit configured to modify a first divider count, wherein the modified divider count programs the modulator circuit.

2. The frequency synthesizer circuit of claim 1 , wherein the control system comprises a phase-frequency detector, a charge pump, a loop filter, a feedback divider, and a voltage controlled oscillator.

3. The frequency synthesizer circuit of claim 2 , wherein the feedback divider comprises a programmable integer divider.

4. The frequency synthesizer circuit of claim 3 , wherein the programmable integer divider operates on an 8-bit count value.

5. The frequency synthesizer circuit of claim 2 , wherein the voltage controlled oscillator generates a differential output signal.

6. The frequency synthesizer circuit of claim 1 , wherein the modulator circuit includes a sigma-delta modulator.

7. The frequency synthesizer circuit of claim 6 , wherein the sigma-delta modulator is a third-order sigma-delta modulator.

8. The frequency synthesizer circuit of claim 7 , wherein the sigma-delta modulator is configured to operate on a 17-bit fraction component.

9. The frequency synthesizer circuit of claim 1 , wherein the selection circuit includes a multiplexer configured to select between sets of least significant bit values.

10. The frequency synthesizer circuit of claim 9 , wherein the selection circuit is configured to select between a first value and a second value.

11. The frequency synthesizer circuit of claim 10 , wherein the first value is programmed by software and the second value is a preconfigured constant.

12. The frequency synthesizer circuit of claim 10 , wherein the first value and second value are programmed by software.

13. A radio-frequency communications subsystem, the subsystem comprising:

an antenna configured to send and receive radio-frequency electromagnetic signals;

a radio-frequency circuit coupled to the antenna;

a resonator configured to provide a frequency reference signal; and

an integrated radio chip coupled the radio-frequency circuit and to the resonator, wherein the integrated radio chip includes circuitry for transmitting and receiving radio frequency signals, the integrated radio chip including:

a system memory configured to store programming instructions and data;

a central processing unit complex configured to program circuitry within the integrated radio chip;

a clock generator configured to generate a reference clock signal;

an integrated radio transceiver circuit configured to process radio-frequency electrical signals; and

a fractional-N frequency synthesizer coupled to the clock generator and to the integrated radio transceiver circuit, wherein the fractional-N frequency synthesizer is configured to substitute at least one programmed least significant bit for an alternate value.

14. The subsystem of claim 13 , wherein the alternate value is programmed by software.

15. The subsystem of claim 13 , wherein the alternate value is a preconfigured constant.

16. A computer-readable medium including instructions that, when executed by a processing unit, cause the processing unit to compute divider values that mitigate fractional spurs in a frequency synthesizer circuit, by performing the steps of:

receiving a desired frequency for the frequency synthesizer circuit to generate;

computing a first divider value for the desired frequency;

examining the first divider value for values that produce fractional spurs in the frequency synthesizer circuit;

substituting at least one least significant bit in the first divider value creating a second divider value that mitigates fractional spurs in the frequency synthesizer circuit; and,

using the second divider value in the frequency synthesizer.

17. The computer-readable medium of claim 16 , wherein the desired frequency is specified as an index value.

18. The computer-readable medium of claim 16 , wherein the desired frequency is specified in cycles per second.

19. The computer-readable medium of claim 16 , wherein the step of determining if the divider value is a pathological fraction comprises determining if the divider value includes a minimum number of zeros in the least significant bit positions.

20. The computer-readable medium of claim 16 , wherein the step of substituting at least one least significant bit comprises substituting the at least one least significant bit with a constant.

21. A fractional-N frequency synthesizer circuit comprising:

a control system configured to generate an oscillating output signal defined by a divider counter;

an adder coupled to the divider counter configured to determine a divider value used by the divider counter by adding a first value and a second value, wherein the first value is an integer component of a fixed-point divider count and the second value is a fractional component of the fixed-point divider count;

a sigma-delta modulator coupled to the adder and configured to provide a signed dither value as the second value to the adder;

a register coupled to the adder configured to store the fixed-point divider count and provide the first value to the adder; and

a multiplexer coupled to the sigma-delta modulator configured to provide a fractional component of the fixed-point divider count wherein the fractional component is selected from either the register or a substitute LSB register.