Optimized lid attach process for thermal management and multi-surface compliant heat removal
View Patent ↗A multi-surface compliant heat removal process includes: identifying one or more components to share a heat rejecting device, applying non-adhesive film to the one or more components, identifying a primary component of the one or more components, and applying phase change material on each of the one or more components other than the primary component. The phase change material is placed on top of the non-adhesive film. The process further includes placing the heat rejecting device on the corresponding one or more components and removing the heat rejecting device from the corresponding one or more components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device, removing the non-adhesive film from the heat rejecting device, placing a heatsink-attach thermal interface material on the one or more components, and placing the heat rejecting device on the corresponding one or more components.
1. A semiconductor package assembly process comprising:
attaching one or more die to a substrate by a die-attach interconnect;
raising a temperature of the one or more die to a target temperature;
placing a lid-attach thermal interface material on the one or more die upon reaching the target temperature;
placing a lid on the substrate to achieve a target bond line thickness of the lid-attach thermal interface material between the one or more die and the lid; and
curing the assembled semiconductor package at a curing temperature.
2. The semiconductor package assembly process of claim 1 , further comprising:
reflowing the die-attach interconnect.
3. The semiconductor package assembly process of claim 1 , further comprising:
flooding the die-attach interconnect with an underfill material.
4. The semiconductor package assembly process of claim 1 , wherein the curing temperature is the same as the target temperature.
5. The semiconductor package assembly process of claim 1 , wherein one or more die exhibit warpage after being attached to the substrate.
6. The semiconductor package assembly process of claim 4 , wherein the target temperature is sufficient to cause the one or more die to become substantially flat.
7. The semiconductor package assembly process of claim 4 , wherein a target bond line thickness of the lid-attach thermal interface material is controlled by the compression of the die and the lid.