Fast ECC memory testing by software including ECC check byte
View Patent ↗The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.
1. A Random Access Memory Controller logic for a memory unit comprising a data section and an Error Correction Code (ECC) memory section, the Random Access Memory Controller logic comprising a functional hardware component implementing a functional component for performing:
(a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving equation (1):
E*X=C, (1)
wherein:
C is a check bit string consisting of m bits, wherein all bits have a logical value of “1”, X is a data pattern consisting of n bits fulfilling said equation (1), E is a known n×m ECC matrix, and wherein n is a number of data bits and m is a number of check bits;
(b) generating a data pattern P 3 by calculating a term (2) or (2′):
P 3 =X XOR P 1 or (2)
P 3 =X XOR P 2, (2′)
wherein P 1 and P 2 are arbitrary data patterns of a same bit length as said X data pattern;
(c) writing said data pattern P 3 into the data section of said memory unit, thus generating respective ECC data;
(d) testing said ECC memory section in an ECC test run procedure by reading out the ECC data associated with said P 3 data patterns; and
(e) indicating an error, if said ECC test run procedure leads to an incorrect result.
2. The Random Access Memory Controller logic according to claim 1 applied with a dynamic memory.
3. The Random Access Memory Controller logic of claim 1 , wherein the functional component further performs:
testing said data section with a preselected data pattern P 1 ; and
testing said data section with a preselected data pattern P 2 , wherein P 2 is the bit complement of P 1 .
4. The Random Access Memory Controller logic of claim 1 , wherein said XOR operation (2) or (2′) is solved for P 1 or P 2 :
P 1 =P 3 XORX
or
P 2 =P 3 XORX
or the combination
P 2 =P 3 XOR (bit complement of X )
and applied for recovering the input pattern P 3 .
5. A computer system comprising a memory unit and a processor, the memory unit comprising a data section and an Error Correction Code (ECC) memory section, and the processor configured to perform:
(a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving an equation (1):
E*X=C, (1)
wherein:
C is a check bit string consisting of m bits, wherein all bits have a logical value of “1”, X is a data pattern consisting of n bits fulfilling said equation (1), E is a known n×m ECC matrix, and wherein n is a number of data bits and m is a number of check bits;
(b) generating a data pattern P 3 by calculating a term (2) or (2′):
P 3 =X XOR P 1 or (2)
P 3 =X XOR P 2, (2′)
wherein P 1 and P 2 are arbitrary data patterns of a same bit length as said X data pattern;
(c) writing said data pattern P 3 into the data section of said memory unit, thus generating respective ECC data;
(d) testing said ECC memory section in an ECC test run procedure by reading out the ECC data associated with said P 3 data patterns; and
(e) indicating an error, if said ECC test run procedure leads to an incorrect result.
6. The computer system of claim 5 , wherein the processor is further configured to perform:
testing said data section with a preselected data pattern P 1 ; and
testing said data section with a preselected data pattern P 2 , wherein P 2 is the bit complement of P 1 .
7. The computer system of claim 5 , wherein said XOR operation (2) or (2′) is solved for P 1 or P 2 :
P 1 =P 3 XORX
or
P 2 =P 3 XORX
or the combination
P 2 =P 3 XOR (bit complement of X )
and applied for recovering the input pattern P 3 .
8. A computer program product stored on a computer usable medium comprising computer readable program means for causing a computer having a memory unit comprising a data section and an Error Correction Code (ECC) memory section to perform:
(a) supplying a data pattern X, that generates a predetermined ECC checksum C by solving equation (1):
E*X=C, (1)
wherein:
C is a check bit string consisting of m bits, wherein all bits have a logical value of “1”, X is a data pattern consisting of n bits fulfilling said equation (1), E is a known n×m ECC matrix, and wherein n is a number of data bits and m is a number of check bits;
(b) generating a data pattern P 3 by calculating a term (2) or (2′):
P 3 =X XOR P 1 or (2)
P 3 =X XOR P 2, (2′)
wherein P 1 and P 2 are arbitrary data patterns of a same bit length as said X data pattern;
(c) writing said data pattern P 3 into the data section of said memory unit, thus generating respective ECC data;
(d) testing said ECC memory section in an ECC test run procedure by reading out the ECC data associated with said P 3 data patterns; and
(e) indicating an error, if said ECC test run procedure leads to an incorrect result.
9. The computer program product of claim 8 , wherein the computer readable program means further cause the computer to perform:
testing said data section with a preselected data pattern P 1 ; and
testing said data section with a preselected data pattern P 2 , wherein P 2 is the bit complement of P 1 .
10. The computer program product of claim 8 , wherein said XOR operation (2) or (2′) is solved for P 1 or P 2 :
P 1 =P 3 XORX
or
P 2 =P 3 XORX
or the combination
P 2=P3 XOR (bit complement of X )
and applied for recovering the input pattern P 3 .