DEVICE WITH A PROCESSOR AND A PERIPHERAL UNIT AND METHOD FOR GENERATING AN ACKNOWLEDGMENT SIGNAL
A device is provided that includes a processor, a peripheral unit, and a first logic, and to a method for generating an acknowledgment signal. The processor is clocked by a processor clock signal, which runs asynchronously to the peripheral clock signal, by which the peripheral unit is clocked. The peripheral unit sends an interrupt request synchronously to the peripheral clock signal to the processor, which thereupon is woken up from its idle state, to process the interrupt request in its working state. After the processing or during the processing of the interrupt request, the processor generates an acknowledgment signal synchronous to the processor clock signal. The first logic generates an acknowledgment signal, which is synchronous to the peripheral clock signal and by which the peripheral unit is informed about the processed interrupt request, from the acknowledgment signal synchronous to the processor clock signal.
1 . A device comprising
a processor that is clocked by a processor clock signal and is woken up from an idle state, based on an interrupt request, to process the interrupt request in a working state, and after the processing or during the processing of the interrupt request the processor generates an acknowledgment signal synchronous to the processor clock signal;
at least one peripheral unit, which is clocked by a peripheral clock signal that runs asynchronously to the processor clock signal, and which sends the interrupt request to the processor synchronously to the peripheral clock signal; and
a first logic that generates an acknowledgment signal, which is synchronous to the peripheral clock signal, and by which the peripheral unit is informed about the processed interrupt request from the acknowledgment signal synchronous to the processor clock signal.
2 . The device according to claim 1 , wherein the first logic has a first flip-flop, which is clocked by the processor clock signal and whose input signal is at least indirectly the acknowledgment signal synchronous to the processor clock signal, and wherein the first logic has a second flip-flop for generating the acknowledgment signal, which is synchronous to the peripheral clock signal and is clocked by the peripheral clock signal and whose input signal is the output signal of the first flip-flop.
3 . The device according to claim 2 , wherein the first logic has a plurality of second flip-flops connected one behind the other, each of which is clocked by the peripheral clock signal, and wherein the output signal of the last connected second flip-flop represents the acknowledgment signal synchronous to the peripheral clock signal.
4 . The device according to claim 1 , wherein a second logic, which generates from the interrupt request, sent synchronously to the peripheral clock signal, an interrupt request that runs synchronously to the processor clock signal and is supplied to the processor.
5 . The device according to claim 4 , wherein the second logic has a shift register whose input signal is the interrupt request sent synchronously to the peripheral clock signal or a signal synchronous to the interrupt request sent to the peripheral clock signal, wherein the second logic has a logic connected downstream to the shift register for detecting an edge of the output signal of the shift register, and wherein the second logic has a flip-flop, which is clocked by the processor clock signal, whose input signal is the output signal of the logic for detecting an edge and whose output signal is the interrupt request running synchronously to the processor clock signal.
6 . The device according to claim 1 , wherein the device determines at least one tire parameter of a tire of a vehicle, the device further comprising at least one sensor for determining the tire parameter, and a transmitter, wherein the processor based on the interrupt request determines the tire parameter via the sensor and generates a message about the tire parameter that the transmitter sends.
7 . A method for generating an acknowledgment signal, the method comprising the steps of:
generating an interrupt request synchronous to a peripheral clock signal by a peripheral unit, which is clocked by the peripheral clock signal;
waking up of a processor based on the interrupt request, so that the processor changes from an idle state to a working state to process the interrupt request, wherein the processor is clocked by a processor clock signal running asynchronously to the peripheral clock signal;
generating an acknowledgment signal synchronous to the processor clock signal after the processor has processed the interrupt request or while the processor is processing the interrupt request; and
generating an acknowledgment signal synchronous to the peripheral clock signal from the acknowledgment signal synchronous to the processor clock signal via a first logic to inform the peripheral unit about the processed interrupt request.
8 . The method according to claim 7 , wherein the first logic has a first flip-flop, which is clocked by the processor clock signal and whose input signal is at least indirectly the acknowledgment signal synchronous to the processor clock signal, and wherein the first logic has a second flip-flop for generating the acknowledgment signal, which is synchronous to the peripheral clock signal and is clocked by the peripheral clock signal and whose input signal is the output signal of the first flip-flop.
9 . The method according to claim 8 , wherein the first logic has a plurality of second flip-flops connected one behind the other, each of which is clocked by the peripheral clock signal, wherein the output signal of the last connected second flip-flop represents the acknowledgment signal synchronous to the peripheral clock signal.
10 . The method according to claim 7 , wherein a second logic generates, from the interrupt request sent synchronously to the peripheral clock signal, an interrupt request that runs synchronously to the processor clock signal and is supplied to the processor.
11 . The method according to claim 10 , wherein the second logic has a shift register whose input signal is the interrupt request sent synchronously to the peripheral clock signal or a signal synchronous to the interrupt request sent to the peripheral clock signal, wherein the second logic has a logic connected downstream to the shift register for detecting an edge of the output signal of the shift register, and wherein the second logic has a flip-flop, which is clocked by the processor clock signal, whose input signal is the output signal of the logic for detecting an edge and whose output signal is the interrupt request running synchronously to the processor clock signal.
12 . The method according to claim 10 , wherein the second logic generates a wake-up signal for the processor from the interrupt request sent synchronously to the peripheral clock.
13 . The method according to claim 7 , wherein the processor clock signal has a higher clock frequency than the peripheral clock signal.
14 . The method according to claim 7 , wherein the processor, the peripheral unit, and the first logic are part of wheel electronics for detecting at least one tire parameter of a tire, to which the wheel electronics are assigned, and wherein the method further comprises the steps:
measuring a tire parameter of the tire by a sensor of the wheel electronics;
generating a message about the tire parameter of the tire by the processor based on an interrupt request; and
transmitting the message by a transmitter of the wheel electronics.