Method for managing memory access and task distribution on a multi-processor storage device
View Patent ↗In a system for reading and writing data, the system including a controller, multiple microprocessor units accessible to the controller, and multiple memory device configurations, each having one dedicated bus connection to individual ones or multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations includes the steps, (a) receiving a request at the controller requiring access of at least one of the memory device configurations, (b) determining at the controller, which microprocessor unit or units will handle the request, (c) handing the request to the selected microprocessor unit or units, (d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units and (e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.
1. In a system for reading and writing data, including a controller, multiple microprocessor units internally bused to the controller, and multiple memory device configurations, each configuration having a dedicated bus connection to multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations, comprising the steps:
(a) receiving a read and write request and data management tasks at the controller requiring access to the memory device configurations;
(b) determining at the controller, a microprocessor unit or units to handle the request for read and write and selecting a separate microprocessor unit or units to handle the data management tasks;
(c) handing the request for read and write and the data management tasks to the microprocessor unit or units determined at step (b);
(d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units;
(e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.
2. The method of claim 1 wherein in step (a) the controller includes a host controller interface and a data flow state machine.
3. The method of claim 2 wherein in step (b) the data flow state machine is responsible for microprocessor unit selection.
4. The method of claim 1 wherein in step (a) the request is received from a computing system over a data network.
5. The method of claim 1 wherein in step (b) in the case of more than one microprocessor unit selected, the request or data management tasks is sent to each microprocessor unit.
6. The method of claim 1 wherein in step (a) the controller includes an onboard microprocessor unit having a dedicated amount of RAM.
7. The method of claim 6 wherein in step (b) the microprocessor unit is responsible for microprocessor unit selection.
8. The method of claim 6 wherein in step (c) the onboard microprocessor unit sends the request or data management tasks to all available microprocessor units.
9. The method of claim 1 wherein in step (d) in the case of more than one microprocessor unit handling the request or data management tasks, each microprocessor unit is assigned a portion of the total number of tasks specified in the request or data management tasks.
10. The method of claim 9 wherein in step (d) the number of microprocessor units is two and one microprocessor unit is assigned to actual reading and writing and the other microprocessor unit is assigned to other data management tasks.
11. The method of claim 10 wherein in step (d) there is one memory device configuration partitioned and one microprocessor unit performs the request on one partition and the other microprocessor unit performs tasks not related to the request received on the other partition.