Nonvolatile semiconductor memory devices with charge injection corner
View Patent ↗An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.
1. A semiconductor device comprising a nonvolatile memory cell, the nonvolatile memory cell including:
a semiconductor substrate;
a first gate dielectric provided over a main surface of the semiconductor substrate;
a charge trap film provided in the first gate dielectric; and
a memory gate electrode provided over the first gate dielectric,
wherein an erase operation of the nonvolatile memory cell is performed such that charges having a first polarity are injected into a corner portion of the charge trap film from a corner portion of the memory gate electrode,
wherein a write operation of the nonvolatile memory cell is performed such that charges having a second polarity opposite the first polarity are injected into the corner portion of the charge trap film from the semiconductor substrate, and
wherein injecting positions of the charges to the charge trap film in the erase and write operations overlap.
2. The semiconductor device according to claim 1 ,
wherein a gate electrode is provided over the main surface of the semiconductor substrate via a second gate dielectric, and
wherein the memory gate electrode has a side-wall configuration provided on a side of a side wall of the gate electrode.
3. The semiconductor device according to claim 2 , wherein the corner portion of the memory gate electrode has an acute angle portion whose angle is smaller than 90°.
4. The semiconductor device according to claim 1 ,
wherein the memory gate electrode includes silicon, and
the corner portion of the memory gate electrode is formed so as to have an acute angle portion whose angle is smaller than 90° by oxidizing a side wall of the memory gate electrode.
5. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate has an n type semiconductor region,
wherein the memory gate electrode includes n type silicon,
wherein holes are injected from the n type semiconductor region of the semiconductor substrate to the charge trap film, and
wherein electrons are injected from the memory gate electrode to the charge trap film.
6. The semiconductor device according to claim 5 , wherein, when electrons are injected from the memory gate electrode to the charge trap film, a negative potential is applied to the memory gate electrode so that an absolute value of an electric field applied to the first gate dielectric including the charge trap film is in a range of 7 MV/cm or more to 11 MV/cm or less.
7. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a p type semiconductor region,
wherein the memory gate electrode includes p type silicon,
wherein electrons are injected from the p type semiconductor region of the semiconductor substrate to the charge trap film, and
wherein holes are injected from the memory gate electrode to the charge trap film.
8. The semiconductor device according to claim 7 , wherein, when holes are injected from the memory gate electrode to the charge trap film, a positive potential is applied to the memory gate electrode so that an absolute value of an electric field applied to the first gate dielectric including the charge trap film is in a range of 7 MV/cm or more to 11 MV/cm or less.
9. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate has a p type semiconductor region,
wherein the memory gate electrode includes n type silicon,
wherein electrons are injected from the p type semiconductor region of the semiconductor substrate to the charge trap film, and
wherein holes are injected from the memory gate electrode to the charge trap film.
10. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate has an n type semiconductor region,
wherein the memory gate electrode includes p type silicon,
wherein holes are injected from the n type semiconductor region of the semiconductor substrate to the charge trap film, and
wherein electrons are injected from the memory gate electrode to the charge trap film.
11. The semiconductor device according to claim 1 , wherein the charge trap film includes silicon nitride.
12. The semiconductor device according to claim 1 , wherein the charge trap film includes aluminum oxide.
13. The semiconductor device according to claim 1 , wherein the charge trap film includes silicon oxynitride.
14. The semiconductor device according to claim 1 , wherein the charge trap film includes a dielectric film containing silicon nanocrystals each having a diameter smaller than a film thickness of the dielectric film.
15. The semiconductor device according to claim 1 , wherein the first gate dielectric has a stacked configuration in which silicon oxide, a charge trap film, and silicon oxide are stacked in this order.
16. The semiconductor device according to claim 1 , wherein the first gate dielectric has a stacked configuration in which silicon oxide and a charge trap film are stacked from a main surface side of the semiconductor substrate in this order.