Receiving device including packet output circuit for outputting control signal

1. A receiving device, comprising:

a receiving unit receiving a first packet from a transmitting device via a network and outputting a second packet included in the first packet; and

a processing unit receiving the second packet and implementing processing based on a receiving side reference clock on the second packet,

wherein the receiving unit comprises a clocking circuit performing a clocking operation synchronously with a network clock, and a packet output circuit outputting the second packet and outputting a control signal indicating normality or abnormality of output timing of the second packet based on a result of comparing a time of the clocking circuit and a time of first time information included in the first packet; and

the processing unit comprises a clock adjusting circuit synchronizing, when the second packet includes second time information indicating a time based on a transmitting side reference clock and when the control signal indicates normality, the receiving side reference clock with the transmitting side reference clock based on a result of comparing a time based on the receiving side reference clock and a time of the second time information,

wherein when the time of the clocking circuit is after the time of the first time information, the packet output circuit outputs the second packet and outputs the control signal indicating abnormality;

when the time of the clocking circuit is before the time of the first time information, the packet output circuit outputs the second packet and outputs the control signal indicating normality after waiting until both the times of the clocking circuit and the time of the first time information match due to a change of the time of the clocking circuit; and

when the time of the clocking circuit matches with the time of the first time information, the packet output circuit outputs the second packet and outputs the control signal indicating normality.

2. The receiving device according to claim 1 , wherein when the second packet includes the second time information and the control signal indicates normality:

the clock adjusting circuit shortens a cycle of the receiving side reference clock when a difference between a time based on the receiving side reference clock and the time of the second time information is beyond a tolerable range and the time based on the receiving side reference clock is before the time of the second time information; and

the clock adjusting circuit lengthens the cycle of the receiving side reference clock when a difference between a time based on the receiving side reference clock and the time of the second time information is beyond a tolerable range and the time based on the receiving side reference clock is after the time of the second time information.

3. The receiving device according to claim 1 , wherein the first time information is incorporated in the first packet by the transmitting device, and indicates a time obtained by adding a maximum delay time generated by packet transmission via the network to a time based on the network clock.

4. The receiving device according to claim 1 , wherein the first time information is incorporated in the first packet by the transmitting device, and indicates a time obtained by adding an average delay time generated by packet transmission via the network to a time based on the network clock.

5. The receiving device according to claim 1 , wherein the second packet is a transport stream packet complying with an MPEG-2 standard; and the processing unit is an MPEG decoding unit implementing decoding processing according to the MPEG-2 standard.