IP Library Patent Application 12127628
Patent Application
App. No. 12/127,628

Method and Apparatus for Parallel Processing Protocol Data Units

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Patent No.
US None
App. No.
12/127,628
Abstract

An apparatus for processing a protocol data unit (PDU) includes a transmit (TX) module, a physical layer controller (PHY), and a reception (RX) module. The TX module is configured to receive a transmit descriptor that comprises a plurality of fields, wherein the fields contain information for preparing a first PDU. The PHY is configured to receive at least a portion of a second PDU into a reception (RX) physical-layer queue, the second PDU having a header. The RX module is configured to receive a receive descriptor, wherein the receive descriptor includes a plurality of fields having information for processing the second PDU. The RX module is further configured to process the second PDU according to the receive descriptor in parallel with the TX module processing the first PDU based on the transmit descriptor.

Claims (55)

1 . A method comprising:

receiving a transmit descriptor at a transmission (TX) module, wherein the transmit descriptor comprises a plurality of fields, the fields containing information for preparing a first protocol data unit (PDU) for transmission;

receiving, at a physical layer controller (PHY), at least a portion of a second PDU into a reception (RX) physical-layer queue, wherein the second PDU comprises a header;

receiving, at a reception (RX) module, a receive descriptor, wherein the receive descriptor comprises a plurality of fields, wherein the plurality of fields comprise information for processing the second PDU; and

processing, in parallel, the first PDU and the second PDU based on the transmit descriptor and the receive descriptor, respectively.

2 . The method of claim 1 , wherein the first PDU and the second PDU are media access control PDUs (MPDUs) for wireless communication according to an Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard.

3 . The method of claim 1 , wherein the TX module and RX module logically reside between the PHY and a media access control (MAC) processor.

4 . The method of claim 1 , further comprising:

generating, at a media access control (MAC) processor, the transmit descriptor for the first PDU;

communicating the header of the second PDU to the MAC processor; and

generating, at the MAC processor, the receive descriptor based on the header of the second PDU.

5 . The method of claim 1 , wherein processing the first PDU and second PDU comprises at least one of:

running a header check sequence (HCS);

running a cyclic redundancy check (CRC);

encrypting data; and

decrypting data.

6 . The method of claim 1 , further comprising writing the first PDU to a transmission (TX) physical-layer queue.

7 . The method of claim 1 , further comprising:

generating, at a media access control (MAC) processor, one or more transmit control parameters for transmitting a burst, the burst comprising the first PDU; and

sending the one or more control parameters to the PHY.

8 . The method of claim 1 , further comprising:

generating, at a media access control (MAC) processor, one or more control parameters for receiving a burst, the burst comprising the second PDU; and

sending the one or more control parameters to the PHY.

9 . An apparatus comprising:

a transmit (TX) module configured to receive a transmit descriptor, wherein the transmit descriptor comprises a plurality of fields, the fields containing information for preparing a first protocol data unit (PDU);

a physical layer controller (PHY) configured to receive at least a portion of a second PDU into a reception (RX) physical-layer queue, wherein the second PDU comprises a header; and

a reception (RX) module configured to:

receive a receive descriptor, wherein the receive descriptor comprises a plurality of fields, wherein the plurality of fields comprise information for processing the second PDU; and

process the second PDU according to the receive descriptor in parallel with the TX module processing the first PDU based on the transmit descriptor.

10 . The apparatus of claim 9 , wherein the first PDU and the second PDU are media access control PDUs (MPDUs) for wireless communication according to an Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard.

11 . The apparatus of claim 9 , wherein the TX module and RX module logically reside between the PHY and a media access control (MAC) processor.

12 . The apparatus of claim 9 , further comprising a media access control (MAC) processor configured to:

generate the transmit descriptor for the first PDU;

receive the header of the second PDU; and

generate the receive descriptor based on the header of the second PDU.

13 . The apparatus of claim 9 , wherein processing the first PDU and second PDU comprises at least one of:

running a header check sequence (HCS);

running a cyclic redundancy check (CRC);

encrypting data; and

decrypting data.

14 . The apparatus of claim 9 , wherein the TX module is further configured to write the first PDU to a transmission (TX) physical-layer queue.

15 . The apparatus of claim 9 , further comprising a media access control (MAC) processor configured to:

generate one or more transmit control parameters for transmitting a burst, the burst comprising the first PDU; and

send the one or more control parameters to the PHY.

16 . The apparatus of claim 9 , further comprising a media access control (MAC) processor configured to:

generate one or more control parameters for receiving a burst, the burst comprising the second PDU; and

send the one or more control parameters to the PHY.

17 . The apparatus of claim 9 , wherein the PHY is further configured to transmit a bust to a communication device, the burst comprising the first PDU.

18 . The apparatus of claim 9 , wherein the PHY is further configured to receive a burst from a communication device, the burst comprising the second PDU.

19 . The apparatus of claim 9 , wherein the RX physical-layer queue is a first-in-first-out (FIFO) queue.

20 . An apparatus comprising:

means for receiving a transmit descriptor at a transmission (TX) module, wherein the transmit descriptor comprises a plurality of fields, each field containing information for preparing a protocol data unit (PDU);

means for receiving, at a physical layer controller (PHY), at least a portion of a second PDU into a reception (RX) physical-layer queue, wherein the second PDU comprises a header;

means for receiving, at a reception (RX) module, a receive descriptor, wherein the receive descriptor comprises a plurality of fields, wherein each of the plurality of fields comprises information for processing the second PDU; and

means for processing, in parallel, the first PDU and the second PDU based on the transmit descriptor and the receive descriptor, respectively.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035439/0602 →
CHANGE OF NAME Recorded Jul 6, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024630/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2010
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 024018/0615 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2008
From: RAJU, KARTIK (NMI); UN, MEHMET (NMI)
To: FUJITSU LIMITED
Reel/Frame 021004/0672 →