IP Library Granted Patent US 7,957,171
Granted Patent B2
US 7,957,171 · App. 12/128,126 · Granted Jun 7, 2011

Associative memory and searching system using the same

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Quick Facts
Patent No.
US 7,957,171
App. No.
12/128,126
Granted
Jun 7, 2011
Kind
B2
Abstract

Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Claims (9)

1. An associative memory comprising:

a memory array configured to compare each of stored multiple reference data with input search data in parallel and to generate multiple comparison current signals representing a result of the comparison; and

an output circuit that at a j-th search of reference data close to the input search data, wherein j is an integer satisfying 1<j≦k wherein k is an integer equal to or greater than 2, the output circuit being configured to exclude j−1 number of reference data searched until the search performed j−1 times from the multiple reference data and to convert the multiple comparison current signals into voltages to detect the reference data closest to the search data from the remaining reference data, while amplifying the converted voltages to execute k times a signal generation operation for generating a j-th output signal.

2. The associative memory of claim 1 , wherein the output circuit comprises:

a first amplifier, during a j-th signal generation operation, configured to convert the multiple comparison current signals generated by the memory array to multiple voltages, to detect remaining voltages other than a voltage representing the reference data j−1-th closest to the search data from the multiple voltages based on a j−1-th feedback signal, and to amplify the detected remaining voltages into a first voltage representing the reference data j-th closest to the search data and a second voltage representing the reference data remote from the search data;

a second amplifier, during the j-th signal generation operation, configured to further amplify the first and second voltages outputted from the first amplifier to generate the j-th output signal; and

a feedback circuit, during the j-th signal generation operation, configured to generate a j−1-th feedback signal based on a j−1-th output signal outputted from the second amplifier and outputting the j−1-th feedback signal to the first amplifier.

3. The associative memory of claim 2 , wherein the first amplifier is configured to invalidate the comparison current signal representing the reference data j−1-th closest to the search data based on the j−1-th feedback signal to detect remaining voltages other than a voltage representing the reference data j−1-th closest to the search data from the multiple voltages.

4. The associative memory of claim 2 , wherein if the remaining voltages other than a voltage representing the reference data j−1-th closest to the search data from the multiple voltages are detected, the first amplifier is configured to set a threshold value for dividing the remaining voltages into first and second voltages, and to compare the respective remaining voltages with the threshold value to amplify the remaining voltages into the first and second voltages.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED ON JANUARY 29, 2019 AT REEL 048373 FRAME 0217 Recorded Sep 22, 2025
From: CRESTLINE DIRECT FINANCE, L.P., AS COLLATERAL AGENT
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 072936/0464 →
RELEASE OF SECURITY INTEREST Recorded Jul 31, 2019
From: CRESTLINE DIRECT FINANCE, L.P.
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 049924/0794 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2010
From: ABEDIN, MD. ANWARUL; KOIDE, TETSUSHI; MATTAUSCH, HANS JUERGEN; TANAKA, YUKI
To: HIROSHIMA UNIVERSITY
Reel/Frame 024604/0855 →