Methods of forming NAND cell units
View Patent ↗Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
1. A method of forming a NAND cell unit, comprising:
forming a plurality of spaced apart gate stacks over a semiconductor substrate; at least one of the gate stacks being a select gate stack, and at least two of the gate stacks being string gate stacks; the at least one select gate stack comprising a first gate dielectric material, a first gate material over the first gate dielectric material, a first electrically insulative material over the first gate material, and a sacrificial material over the first electrically insulative material; the string gate stacks comprising a second gate dielectric material, a second gate material over the second gate dielectric material, a second electrically insulative material over the second gate material, and the sacrificial material over the second electrically insulative material;
removing the sacrificial material from the at least one select gate stack and from the string gate stacks;
etching through the first electrically insulative material to the first gate material; and
after etching through the first electrically insulative material, forming a conductive material over the at least one select gate stack and over the string gate stacks, the conductive material physically contacting the first gate material and being separated from the second gate material by the second electrically insulative material.
2. The method of claim 1 wherein the first and second gate materials consist of conductively-doped silicon, and wherein the conductive material comprises at least one metal.
3. The method of claim 1 wherein the first and second gate materials consist of conductively-doped silicon, wherein the second gate material consists of p-type doped silicon, wherein the conductive material comprises one or both of titanium nitride and tantalum nitride.
4. The method of claim 3 wherein the conductive material has a thickness of from about 10 Å to about 150 Å.
5. The method of claim 3 wherein the conductive material has a thickness of from about 15 Å to about 50 Å.
6. The method of claim 1 wherein:
the first gate material consists of conductively-doped silicon;
the second gate material comprises at least one charge-trapping composition; and
the conductive material comprises at least one metal.
7. The method of claim 1 wherein the first and second gate materials are compositionally different from one another.
8. The method of claim 1 wherein:
the first and second gate dielectric materials are compositionally the same as one another; and
the first and second electrically insulative materials are compositionally the same as one another.
9. The method of claim 1 wherein the first gate dielectric material comprises a plurality of discrete layers of insulative material.
10. The method of claim 1 wherein the second gate dielectric material comprises a plurality of discrete layers of insulative material.