Field-effect transistor (FET) with embedded diode

1. A Field-Effect Transistor (FET) comprising:

a first portion;

a second portion separated from the first portion by a gap;

a thermal feedback resistor connected in series with a pair of diodes embedded within the gap between the first and second portions forming part of a thermal compensation bias network, the thermal feedback resistor setting a current drawn by the thermal compensation bias network and the diodes sensing changes in a localized temperature of the FET; and

an electrical isolation circuit electrically connected to a gate operating to provide active thermal compensation with the thermal compensation bias network.

2. A FET in accordance with claim 1 further comprising gate fingers and wherein the gap is between gate fingers of the first portion and gate fingers of the second portion.

3. A FET in accordance with claim 1 wherein the thermal compensation bias network is configured to compensate for a positive temperature coefficient.

4. A FET in accordance with claim 1 wherein the thermal compensation bias network is configured to provide a localized negative feedback.

5. A FET in accordance with claim 1 wherein the thermal feedback resistor is an implanted resistor.

6. A FET in accordance with claim 1 wherein the thermal feedback resistor is a film resistor.

7. A FET in accordance with claim 1 wherein the first and second portions comprise first and second halves of a body and the pair of diodes is embedded within the body in the gap between the first and second halves.

8. A FET in accordance with claim 1 wherein the gap is provided along a middle area between the first and second portions.

9. A FET in accordance with claim 1 wherein the gap defines a channel between the first and second portions.

10. A Field-Effect Transistor (FET) array comprising:

a plurality of FETs;

an electrical isolation circuit electrically connected between and in direct contact with the plurality of FETs and that electrically isolates a pair of adjacent FETs, the electrical isolation circuit including a single capacitor connected to a gate of each of the pair of adjacent FETs; and

at least one diode embedded within each of the plurality of FETs.

11. A FET array in accordance with claim 10 further comprising at least one resistor connected to the at least one diode embedded within each of the plurality of FETs, and wherein the at least one diode and the at least one resistor are thermally coupled to the FETs.

12. A FET array in accordance with claim 11 wherein the at least one diode and the at least one resistor comprise a negative thermal feedback circuit.

13. A FET array in accordance with claim 10 wherein a gate of each of the FETs is DC isolated to provide electrical gate bias isolation with the electrical isolation circuit.

14. A FET array in accordance with claim 13 wherein the electrical isolation circuit comprises a pair of resistors in operational electrical connection with the capacitor in an odd mode oscillation suppression configuration and having individual active FET thermal compensation.

15. A FET array in accordance with claim 10 further comprising a gap between first and second portions of each of the FETs, and wherein the at least one diode is embedded within the gap.

16. A FET array in accordance with claim 10 wherein the at least one diode is configured to provide individual FET thermal compensation.

17. A FET array in accordance with claim 16 wherein the plurality of FETs comprise at least sixteen FETs.