IP Library Granted Patent US 8,650,364
Granted Patent B2
US 8,650,364 · App. 12/128,596 · Granted Feb 11, 2014

Processing system with linked-list based prefetch buffer and methods for use therewith

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Quick Facts
Patent No.
US 8,650,364
App. No.
12/128,596
Granted
Feb 11, 2014
Kind
B2
Abstract

A processing device includes a memory and a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory. A prefetch memory interface prefetches prefetch data to a prefetch buffer, retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list.

Claims (35)

1. A video processing system for producing a processed video signal from a video signal based on video data, the video processing device comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory, wherein the read data and the write data include the video data;

a prefetch memory interface coupled to the processor and the memory, that prefetches prefetch data to a prefetch buffer, that retrieves the read data from the prefetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list, wherein the prefetch buffer includes a plurality of entries having a status field that selectively indicates an unload pending status, and wherein the prefetch memory interface includes a prefetch request generator that exclusively selects prefetch data during a time period that corresponds to a programmable prefetch window.

2. The video processing system of claim 1 wherein the plurality of entries are linked via the linked list.

3. The video processing system of claim 2 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

4. The video processing system of claim 2 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

5. The video processing system of claim 2 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

6. A video processing system for processing the video data comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory, wherein the read data and the write data include video data;

a prefetch memory interface coupled to the processor and the memory, that pre fetches pre fetch data to a pre fetch buffer, that retrieves the read data from the pre fetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein the prefetch buffer is managed via a linked list, wherein the prefetch buffer includes a plurality of entries having a status field that selectively indicates an unload pending status, and wherein the prefetch memory interface includes a prefetch request generator that exclusively selects prefetch data during a time period that corresponds to a programmable prefetch window.

7. The video processing system of claim 6 wherein the plurality of entries are linked via the linked list.

8. The video processing system of claim 7 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

9. The video processing system of claim 7 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

10. The video processing system of claim 7 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

11. A method for processing video data comprising:

generating a plurality of read commands for reading read data from a memory, wherein the read data and the write data include the video data;

prefetching prefetch data to a prefetch buffer, wherein the prefetch buffer includes a plurality of entries having a status field that selectively indicates an unload pending status, and wherein prefetching the prefetch data includes selecting prefetch data exclusively during a time period that corresponds to a programmable prefetch window;

managing the prefetch buffer via a linked list;

retrieving the read data from the prefetch buffer when the read data is included in the prefetch buffer; and

retrieving the read data from the memory when the read data is not included in the prefetch buffer.

12. The method of claim 11 wherein the prefetch buffer includes a plurality of entries that are linked via the linked list.

13. The method of claim 12 wherein the plurality of entries are divided into a set of allocated entries and a set of free entries.

14. The method of claim 12 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

15. The method of claim 12 wherein each of the plurality of entries includes a tag that indicates the identity of the pre fetch data.

16. A video processing device for processing video data comprising:

a memory;

a processor that generates a plurality of read commands for reading read data from the memory and a plurality of write commands for writing write data to the memory, wherein the read data and the write data include the video data;

a prefetch memory interface coupled to the processor and the memory, that prefetches pre fetch data to a pre fetch buffer, that retrieves the read data from the pre fetch buffer when the read data is included in the prefetch buffer, and that retrieves the read data from the memory when the read data is not included in the prefetch buffer, wherein a plurality of entries in the prefetch buffer are managed via state transition among a plurality of entry states, wherein the prefetch buffer includes a plurality of entries having a status field that selectively indicates an unload pending status, and wherein the prefetch memory interface includes a prefetch request generator that exclusively selects prefetch data during a time period that corresponds to a programmable prefetch window.

17. The processing system of claim 16 wherein the pre fetch memory interface includes a tag and buffer server that centrally manages the entries in the prefetch buffer.

18. The processing system of claim 16 wherein each of the status field that indicates one of the plurality of entry states.

19. The processing system of claim 16 wherein the plurality of entries are linked via a linked list.

20. The processing system of claim 19 wherein each of the plurality of entries includes a linked list pointer that indicates a neighboring entry in the linked list.

21. The processing system of claim 16 wherein each of the plurality of entries includes a tag that indicates the identity of the prefetch data.

Assignments (1)
RELEASE OF SECURITY INTEREST Recorded Aug 18, 2017
From: COMERICA BANK
To: VIXS SYSTEMS, INC.
Reel/Frame 043601/0817 →