Array substrate and method of manufacturing the same

1. An array substrate of a thin film transistor liquid crystal display comprising:

a substrate; and

a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the plurality of gate lines intersecting the plurality of data lines to define a plurality of pixel regions that are arranged in rows, each pixel region comprising a thin film transistor, a pixel electrode, and a thin film diode,

wherein with respect to each pixel region in a row, the pixel electrode is connected with the gate line used for the pixel regions in a present row through the thin film transistor and directly connected with the gate line used for the pixel regions in a previous row through the thin film diode.

2. The array substrate according to claim 1 , wherein the thin film diode of each pixel region comprises:

a first gate electrode formed on the substrate and connected with the gate line in the present row;

a gate insulating layer formed on the first gate electrode, covering the entire substrate, and formed with a via hole over the first gate electrode;

a first amorphous silicon layer formed on the gate insulating layer and connected with the first gate electrode through the via hole in the gate insulating layer;

a first n 30 amorphous silicon layer formed on the first amorphous silicon layer;

a metal electrode layer formed on the first n 30 amorphous silicon layer and positioned over the first gate electrode;

a passivation layer formed on the metal electrode layer, covering the entire substrate, and formed with a first via hole through which the pixel electrode is connected with the metal electrode layer.

3. The array substrate according to claim 2 , wherein the thin film transistor of each pixel region comprises:

a second gate electrode form on a substrate and connected with the gate line of the previous row;

the gate insulating layer formed on the second gate electrode and covering the entire substrate;

a second amorphous silicon layer formed on the gate insulating layer and positioned over the second gate electrode;

a second n 30 amorphous silicon layer formed on the second amorphous silicon layer;

a source/drain electrode layer formed on the second n 30 amorphous silicon layer and positioned over the second gate electrode with a channel region being formed between source and drain electrodes of the source/drain electrode layer;

the passivation layer formed on the source/drain electrode layer, covering the entire substrate, and formed with a second via hole through which pixel electrode is connected with the drain electrode of the source/drain electrode layer.

4. The array substrate according to claim 2 , wherein the first gate electrode is formed of a material selected from Mo, Al, Al-Ni alloy, Mo—W alloy, Cr, Cu, and any combination thereof.

5. The array substrate according to claim 2 , wherein the metal electrode layer is formed of a material selected from Mo, Al, Al—Ni alloy, Mo—W alloy, Cr, Cu, and any combination thereof.

6. The array substrate according to claim 3 , wherein the passivation layer is formed of silicon nitride.

7. The array substrate according to claim 3 , wherein the pixel electrode is formed of indium tin oxide.

8. The array substrate according to claim 1 , wherein each pixel region consists of a single thin film diode which directly connects the pixel electrode to the gate line used for the pixel regions in the previous row.