IP Library Granted Patent US 7,860,044
Granted Patent B2
US 7,860,044 · App. 12/130,253 · Granted Dec 28, 2010

Methods and apparatus for providing synchronization in a multi-channel communication system

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Quick Facts
Patent No.
US 7,860,044
App. No.
12/130,253
Granted
Dec 28, 2010
Kind
B2
Abstract

A multi-channel processing module is arranged in series with multiple channels of a communication system. The processing module synchronizes downstream symbols among the channels, and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel. The synchronization of downstream symbols among the channels and the synchronization of downstream symbols for at least the given channel with upstream symbols for that channel are collectively achieved by adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths in the multi-channel processing module. The channels may comprise respective subscriber lines of a DSL communication system.

Claims (58)

1. A method of synchronizing a plurality of communication channels of a communication system, the method comprising the steps of:

synchronizing downstream symbols among the plurality of channels; and

synchronizing downstream symbols for at least a given one of the channels with upstream symbols for that channel;

wherein the synchronizing steps collectively comprise adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths, for each of two or more of the channels, in a multi-channel processing module arranged in series with the plurality of channels; and

wherein the symbols of a given one of the channels are detected by detecting an associated cyclic extension in a bypass configuration in which downstream and upstream processing elements associated with the given channel are bypassed.

2. The method of claim 1 wherein the communication system comprises a DSL system and the channels correspond to respective subscriber lines of the DSL system.

3. The method of claim 1 wherein the synchronizing steps comprise synchronizing the symbols relative to a common reference shared by the channels.

4. The method of claim 3 wherein the common reference comprises a common time reference having pulses which occur at intervals given by N+G, where N denotes length of an information-carrying part of a symbol and G denotes length of a cyclic extension of the symbol.

5. The method of claim 1 wherein an additional adjustable delay element is controlled to facilitate detection of the cyclic extension.

6. An article of manufacture comprising a processor-readable non-transitory storage medium having embodied therein executable program instructions which when executed by a processor perform the steps of the method of claim 1 .

7. An apparatus for use in synchronizing a plurality of channels of a communication system, the apparatus comprising:

a processing device implementing a multi-channel processing module arranged in series with each of the plurality of channels, the multi-channel processing module being configured to synchronize downstream symbols among the plurality of channels, and to synchronize downstream symbols for at least a given one of the channels with upstream symbols for that channel;

the multi-channel processing module comprising downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths for each of two or more of the channels;

wherein the multi-channel processing module synchronizes downstream symbols among the plurality of channels and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel by adjusting the downstream and upstream adjustable delay elements; and

wherein the symbols of a given one of the channels are detected by detecting an associated cyclic extension in a bypass configuration in which downstream and upstream processing elements associated with the given channel are bypassed.

8. The apparatus of claim 7 wherein the multi-channel processing module comprises a multi-line processing module associated with an access multiplexer of a DSL system.

9. The apparatus of claim 8 wherein the multi-line processing module is implemented within the access multiplexer.

10. The apparatus of claim 8 wherein the multi-line processing module is implemented as an external module coupled to the access multiplexer.

11. The apparatus of claim 8 wherein the multi-line processing module synchronizes the symbols relative to a common reference shared by the channels.

12. The apparatus of claim 11 wherein the common reference comprises a common time reference having pulses which occur at intervals given by N+G, where N denotes length of an information-carrying part of a symbol and G denotes length of a cyclic extension of the symbol.

13. A method of synchronizing a plurality of communication channels of a communication system, the method comprising the steps of:

synchronizing downstream symbols among the plurality of channels; and

synchronizing downstream symbols for at least a given one of the channels with upstream symbols for that channel;

wherein the synchronizing steps collectively comprise adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths, for each of two or more of the channels, in a multi-channel processing module arranged in series with the plurality of channels;

wherein the common reference comprises a common time reference having pulses which occur at intervals given by N+G, where N denotes length of an information-carrying part of a symbol and G denotes length of a cyclic extension of the symbol; and

wherein the synchronizing steps comprise setting delays of the downstream and upstream adjustable delay elements for a given one of the channels such that a round-trip delay for that channel is approximately given by an integer multiple of N+G.

14. A method of synchronizing a plurality of communication channels of a communication system, the method comprising the steps of:

synchronizing downstream symbols among the plurality of channels; and

synchronizing downstream symbols for at least a given one of the channels with upstream symbols for that channel;

wherein the synchronizing steps collectively comprise adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths, for each of two or more of the channels in a multi-channel processing module arranged in series with the plurality of channels;

wherein the common reference comprises a common time reference having pulses which occur at intervals given by N+G, where N denotes length of an information-carrying part of a symbol and G denotes length of a cyclic extension of the symbol; and

wherein the synchronizing steps comprise setting delays of the downstream and upstream adjustable delay elements for a given one of the channels such that a sum of a downstream delay T DS introduced by the downstream adjustable delay element and an upstream delay T US introduced by the upstream adjustable delay element is approximately given by an integer multiple of N+G.

15. A method of synchronizing a plurality of communication channels of a communication system, the method comprising the steps of:

synchronizing downstream symbols among the plurality of channels; and

synchronizing downstream symbols for at least a given one of the channels with upstream symbols for that channel;

wherein the synchronizing steps collectively comprise adjusting downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths, for each of two or more of the channels, in a multi-channel processing module arranged in series with the plurality of channels; and

wherein the downstream and upstream adjustable delay elements are implemented in respective pre-DTDO and pre-UTDO modules of a multi-line processing module of the communication system, where DTDO denotes downstream time-domain operations and UTDO denotes upstream time-domain operations.

16. An apparatus for use in synchronizing a plurality of channels of a communication system, the apparatus comprising:

a processing device implementing a multi-channel processing module arranged in series with each of the plurality of channels, the multi-channel processing module being configured to synchronize downstream symbols among the plurality of channels, and to synchronize downstream symbols for at least a given one of the channels with upstream symbols for that channel;

the multi-channel processing module comprising downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths for each of two or more of the channels;

wherein the multi-channel processing module synchronizes downstream symbols among the plurality of channels and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel by adjusting the downstream and upstream adjustable delay elements;

wherein the common reference comprises a common time reference having pulses which occur at intervals given by N+G, where N denotes length of an information-carrying part of a symbol and G denotes length of a cyclic extension of the symbol; and

wherein the multi-channel processing module is configured to set delays of the downstream and upstream adjustable delay elements for a given one of the channels such that a round-trip delay for that channel is approximately given by an integer multiple of N+G.

17. An apparatus for use in synchronizing a plurality of channels of a communication system, the apparatus comprising;

a processing device implementing a multi-channel processing module arranged in series with each of the plurality of channels, the multi-channel processing module being configured to synchronize downstream symbols among the plurality of channels and to synchronize downstream symbols for at least a given one of the channels with upstream symbols for that channel;

the multi-channel processing module comprising downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths for each of two or more of the channels;

wherein the multi-channel processing module synchronizes downstream symbols among the plurality of channels and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel by adjusting the downstream and upstream adjustable delay elements; and

wherein the downstream and upstream adjustable delay elements are implemented in respective pre-DTDO and pre-UTDO modules of the multi-line processing module, where DTDO denotes downstream time-domain operations and UTDO denotes upstream time-domain operations.

18. A communication system, comprising:

a first transceiver;

a plurality of additional transceivers configured to communicate with the first transceiver over respective ones of a plurality of communication channels; and

a multi-channel processing module coupled between the first transceiver and the plurality of additional transceivers in series with each of the plurality of channels;

the multi-channel processing module being configured to synchronize downstream symbols among the plurality of channels, and to synchronize downstream symbols for at least a given one of the channels with upstream symbols for that channel;

the multi-channel processing module comprising downstream and upstream adjustable delay elements associated with respective downlink and uplink signal paths for each of two or more of the channels;

wherein the multi-channel processing module synchronizes downstream symbols among the plurality of channels and synchronizes downstream symbols for at least a given one of the channels with upstream symbols for that channel by adjusting the downstream and upstream adjustable delay elements; and

wherein the symbols of a given one of the channels are detected by detecting an associated cyclic extension in a bypass configuration in which downstream and upstream processing elements associated with the given channel are bypassed.

19. The communication system of claim 18 wherein the first transceiver comprises a central office of a DSL system.

20. The communication system of claim 18 wherein the additional transceivers comprise respective customer premises equipment elements of a DSL system.

Assignments (10)
CHANGE OF NAME Recorded Jan 27, 2022
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058871/0336 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2018
From: NOKIA USA INC.
To: PROVENANCE ASSET GROUP, LLC
Reel/Frame 047791/0566 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2018
From: NOKIA USA INC.
To: PROVENANCE ASSET GROUP HOLDINGS LLC
Reel/Frame 049139/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2018
From: PROVENANCE ASSET GROUP LLC
To: FACEBOOK, INC.
Reel/Frame 047190/0360 →
PARTIAL RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 043967/0001 Recorded Aug 30, 2018
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: PROVENANCE ASSET GROUP, LLC
Reel/Frame 046981/0600 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP LLC
To: NOKIA USA INC.
Reel/Frame 043879/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2017
From: NOKIA TECHNOLOGIES OY; NOKIA SOLUTIONS AND NETWORKS BV; ALCATEL LUCENT SAS
To: PROVENANCE ASSET GROUP LLC
Reel/Frame 043877/0001 →
SECURITY INTEREST Recorded Sep 13, 2017
From: PROVENANCE ASSET GROUP HOLDINGS, LLC; PROVENANCE ASSET GROUP, LLC
To: CORTLAND CAPITAL MARKET SERVICES, LLC
Reel/Frame 043967/0001 →
MERGER Recorded Nov 10, 2010
From: LUCENT TECHNOLOGIES INC.
To: ALCATEL-LUCENT USA INC.
Reel/Frame 025340/0919 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2008
From: ASHIKHMIN, ALEXEI E.; CHOW, HUNGKEI KEITH; DE LIND VAN WIJNGAARDEN, ADRIAAN J.; HELLENTHAL, JAN WILLEM; JENNEN, JEAN GERARDUS LEONARDUS; KRAMER, GERHARD GUENTER THEODOR; POSTHUMA, CARL ROBERT; VAN TELLINGEN, HARMANUS; WHITING, PHILIP ALFRED; ZIVKOVIC, MIROSLAV
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 021460/0068 →