IP Library Granted Patent US 8,241,950
Granted Patent B2
US 8,241,950 · App. 12/130,828 · Granted Aug 14, 2012

System and method to manufacture an implantable electrode

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Quick Facts
Patent No.
US 8,241,950
App. No.
12/130,828
Granted
Aug 14, 2012
Kind
B2
Abstract

The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Claims (38)

1. A method of building a series of encapsulated devices, the method comprising the steps of:

providing a base having a frame portion and a center portion;

building a preliminary electrode structure coupled to the base, wherein the step of building the preliminary electrode structure coupled to the base includes the step of building a plurality of layers coupled to the base, and wherein the step of building a plurality of layers coupled to the base further includes the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site;

removing a portion of the preliminary electrode structure, thereby forming a series of electrode devices and a plurality of bridges from a remaining portion of the preliminary electrode structure, wherein the series of electrode devices are coupled to the center portion of the base, and wherein the plurality of bridges are coupled to the frame portion of the base and to the series of electrode devices;

removing the center portion of the base such that the frame portion defines an open region, wherein the series of electrode devices hang from the plurality of bridges in the open region defined by the frame; and

encapsulating the series of electrode devices.

2. The method of claim 1 wherein the step of providing a base having a frame portion and a center portion includes the step of providing a silicon wafer.

3. The method of claim 1 wherein the step of providing a base having a frame portion and a center portion includes the step of removing a portion of the base such that the base defines a trench that separates the center portion of the base from the frame portion of the base.

4. The method of claim 3 wherein the step of removing a portion of the base such that the base defines a trench that separates the center portion of the base from the frame portion of the base is performed through a deep reactive ion etching (DRIE) process.

5. The method of claim 1 wherein the step of building a plurality of layers coupled to the base includes the step of building a plurality of layers of material chosen from the group consisting of silicon, metal, polymer, and any combination thereof.

6. The method of claim 1 further comprising the step of removing a portion of the encapsulation from the series of electrode devices to expose the electrode site.

7. The method of claim 6 further comprising the step of electroplating the exposed electrode site.

8. The method of claim 1 wherein the step of removing a portion of the preliminary electrode structure to form a series of electrode devices and a plurality of bridges is performed through a reactive ion etching (RIE) process.

9. The method of claim 1 wherein the step of removing the center portion of the base such that the frame portion defines an open region includes the steps of creating a mask on the base and patterning the mask to expose the frame portion of the base.

10. The method of claim 9 wherein the step of removing the center portion of the base such that the frame portion defines an open region further includes the step of modifying the frame portion of the base such that it behaves as an etch stop.

11. The method of claim 10 wherein the step of modifying the frame portion of the base is performed through boron diffusion.

12. The method of claim 10 wherein the step of removing the center portion of the base such that the frame portion defines an open region is performed with a wet etchant that removes the unmodified portions of the base.

13. The method of claim 1 wherein the step of encapsulating the series of electrode devices includes the step of encapsulating the series of electrode devices, the plurality of bridges, and the frame portion of the base in a conformal coat of a coating.

14. The method of claim 1 further comprising the step of cutting the plurality of bridges, thereby removing the series of electrode devices from the plurality of bridges and from the frame portion of the base.

15. The method of claim 1 , wherein the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site includes building a conductive lead adjacent to a dielectric stack that provides electrical insulation to the conductive lead, wherein the dielectric stack includes material chosen from the group consisting of silicon, metal, polymer, and any combination thereof.

16. The method of claim 15 , wherein the step of building a conductive lead adjacent to a dielectric stack that provides electrical insulation to the conductive lead includes building a dielectric stack including material chosen from the group consisting of vapor deposited silicon dioxide and vapor deposited silicon nitride.

17. The method of claim 1 , wherein the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site includes building an electrode site in a center layer sandwiched between layers of polymer.

18. The method of claim 1 , wherein the step of building a plurality of layers coupled to the base includes building a plurality of layers such that the electrode device and the plurality of bridges include the same plurality of layers.

19. The method of claim 18 , wherein the step of building a conductive lead adjacent to a dielectric stack that provides electrical insulation to the conductive lead includes building a dielectric stack including material chosen from the group consisting of vapor deposited silicon dioxide and vapor deposited silicon nitride.

20. A method of encapsulating a semiconductor device, the method comprising the steps of:

providing a wafer that defines an open region;

building a semiconductor device including a plurality of layers, wherein building the semiconductor device includes building a preliminary structure coupled to the wafer and removing a portion of the preliminary structure, thereby forming the semiconductor device from a remaining portion of the preliminary structure, wherein the step of building a preliminary structure coupled to the wafer includes the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site;

building a plurality of bridges coupled to the wafer and coupled to the semiconductor device such that the semiconductor device hangs from the plurality of bridges in the open region defined by the wafer, wherein the semiconductor device and the plurality of bridges include the same plurality of layers;

encapsulating the semiconductor device; and

after encapsulating the series of electrode devices, cutting the plurality of bridges, thereby removing the series of electrode devices from the plurality of bridges.

21. The method of claim 20 wherein the step of providing a wafer that defines an open region includes the steps of:

providing a wafer having a frame portion and a center portion;

modifying the frame portion of the wafer such that it behaves as an etch stop; and

removing the center portion of the wafer such that the frame portion defines an open region.

22. The method of claim 21 , wherein the step of modifying the frame portion of the wafer is performed through boron diffusion.

23. The method of claim 20 wherein the step of encapsulating the semiconductor device includes the step of encapsulating the semiconductor device, the plurality of bridges, and the wafer in a conformal coat of a coating.

24. The method of claim 20 , wherein the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site includes building a conductive lead adjacent to a dielectric stack that provides electrical insulation to the conductive lead, wherein the dielectric stack includes material chosen from the group consisting of silicon, metal, polymer, and any combination thereof.

25. The method of claim 20 , wherein the step of building a conductive lead and at least one of a stimulation electrode site and a recording electrode site includes building an electrode site in a center layer sandwiched between layers of polymer.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Oct 12, 2022
From: MANUFACTURERS AND TRADERS TRUST COMPANY (AS ADMINISTRATIVE AGENT)
To: GREATBATCH, INC.; GREATBATCH LTD.; ELECTROCHEM SOLUTIONS, INC.; NEURONEXUS TECHNOLOGIES, INC.; GREATBATCH-GLOBE TOOL, INC.; PRECIMED INC.; MICRO POWER ELECTRONICS, INC.
Reel/Frame 061659/0858 →
RELEASE OF SECURITY INTEREST Recorded Jan 6, 2022
From: MANUFACTURERS AND TRADERS TRUST COMPANY (AS ADMINISTRATIVE AGENT)
To: GREATBATCH, INC.; GREATBATCH LTD.; ELECTROCHEM SOLUTIONS, INC.; NEURONEXUS TECHNOLOGIES, INC.; GREATBATCH-GLOBE TOOL, INC.; PRECIMED INC.; MICRO POWER ELECTRONICS, INC.
Reel/Frame 060938/0069 →
RELEASE OF SECURITY INTEREST Recorded Jan 6, 2022
From: MANUFACTURERS AND TRADERS TRUST COMPANY (AS ADMINISTRATIVE AGENT)
To: GREATBATCH, LTD; ELECTROCHEM SOLUTIONS, INC.; NEURONEXUS TECHNOLOGIES, INC.; MICRO POWER ELECTRONICS, INC.
Reel/Frame 058649/0728 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2016
From: MANUFACTURERS AND TRADERS TRUST COMPANY
To: GREATBATCH LTD.; GREATBATCH INC.; QIG GROUP LLC; NEURONEXUS TECHNOLOGIES, INC.; MICRO POWER ELECTRONICS, INC.; ELECTROCHEM SOLUTIONS, INC.
Reel/Frame 039132/0773 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNORS NAME PREVIOUSLY RECORDED ON REEL 037435 FRAME 0512. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 25, 2016
From: GREATBATCH LTD.
To: NEURONEXUS TECHNOLOGIES, INC.
Reel/Frame 037579/0177 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2016
From: GREATBATCH, LTD.
To: NEURONEXUS TECHNOLOGIES, INC.
Reel/Frame 037435/0512 →
SECURITY INTEREST Recorded Oct 27, 2015
From: GREATBATCH, INC.; GREATBATCH LTD.; ELECTROCHEM SOLUTIONS, INC.; NEURONEXUS TECHNOLOGIES, INC.; GREATBATCH-GLOBE TOOL, INC.; PRECIMED INC.; MICRO POWER ELECTRONICS, INC.
To: MANUFACTURERS AND TRADERS TRUST COMPANY
Reel/Frame 036980/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2015
From: NEURONEXUS TECHNOLOGIES, INC.
To: GREATBATCH LTD.
Reel/Frame 036701/0156 →
GRANT OF SECURITY INTEREST Recorded Sep 23, 2013
From: GREATBATCH LTD; ELECTROCHEM SOLUTIONS, INC.; NEURONEXUS TECHNOLOGIES, INC.; MICRO POWER ELECTRONICS, INC.
To: MANUFACTURERS AND TRADERS TRUST COMPANY (AS ADMINISTRATIVE AGENT FOR THE SECURED PARTIES)
Reel/Frame 031290/0278 →
GRANT OF SECURITY INTEREST Recorded May 24, 2012
From: NEURONEXUS TECHNOLOGIES, INC.
To: MANUFACTURERS AND TRADERS TRUST COMPANY
Reel/Frame 028274/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2009
From: PELLINEN, DAVID S.; HETKE, JAMILLE F.; KIPKE, DARYL R.; KONG, K. C.; VETTER, RIO J.; GULARI, MAYURACHAT
To: NEURONEXUS TECHNOLOGIES INC.
Reel/Frame 022789/0129 →