IP Library › Patent Application 12131016
Patent Application
App. No. 12/131,016

Methods for Fabricating Semiconductor Devices

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Quick Facts
Patent No.
US None
App. No.
12/131,016
Abstract

Methods of fabricating a gate-insulating layer of a dual-gate semiconductor device are disclosed. A disclosed method comprises sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area; forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate; forming at least one device isolation layer by depositing an oxide layer in the trench and planarizing the oxide layer; removing the nitride layer and the buffer oxide layer remaining on the high voltage device area; forming a first gate-insulating layer on the high voltage device area; removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and forming a second gate-insulating layer on the low voltage device area.

Claims (20)

1 . A method of fabricating a semiconductor device comprising:

sequentially forming a buffer oxide layer and a nitride layer on a semiconductor substrate having at least one high voltage device area and at least one low voltage device area;

forming at least one trench by selectively removing at least one portion of the buffer oxide layer, the nitride layer and the semiconductor substrate;

depositing an oxide layer in the trench and planarizing the oxide layer;

performing a nitrogen ion implantation on an entire surface of the semiconductor substrate;

removing the nitride layer and the buffer oxide layer remaining on the high voltage device area;

forming a first gate-insulating layer on the high voltage device area;

removing the nitride layer and the buffer oxide layer remaining on the low voltage device area; and

forming a second gate-insulating layer on the low voltage device area.

2 . The method as defined in claim 1 , wherein the nitrogen ion implantation is performed before the nitride layer and the buffer oxide layer are removed from either the high voltage device area or the low voltage device area.

3 . The method as defined in claim 1 , wherein the nitrogen ion implantation is performed after the nitride layer and the buffer oxide layer are removed from the high voltage device area and before the first gate-insulating layer is formed on the high voltage device area.

4 . The method as defined in claim 1 , wherein the nitrogen ions are implanted into the semiconductor substrate at a concentration between about 1E13 ions/cm 2 and about 1E14 ions/cm 2 at an energy level between about 5 keV and about 20 keV.

5 . The method as defined in claim 1 , wherein the buffer oxide layer has a thickness between about 40 Å and about 150 Å and the nitride layer has a thickness between about 600 Å and about 1500 Å.

6 . The method as defined in claim 1 , wherein removing the nitride layer and the buffer oxide layer remaining on the high voltage device area comprises wet-etching the nitride layer with a mixture of purified water and phosphoric acid, and removing the buffer oxide layer with dilute HF.

7 . The method as defined in claim 1 , wherein the first gate-insulating layer has a thickness between about 50 Å and about 150 Å, and the second gate-insulating layer has a thickness between about 20 Å and about 30 Å.

8 . The method as defined in claim 1 , wherein the first gate-insulating layer is formed by heat-treating the semiconductor substrate for about 15 to about 30 minutes in a NO atmosphere at a temperature between about 850° C. and about 900° C.

9 . The method as defined in claim 1 , wherein the second gate-insulating layer is formed by heat-treating the semiconductor substrate for about 5 to about 15 minutes in a NO atmosphere at a temperature between about 850° C. and about 900° C.

10 . The method as defined in claim 1 , wherein the forming the first gate-insulating layer is performed next to the removing the nitride layer and the buffer oxide layer.

11 . The method as defined in claim 1 , wherein the first gate-insulating layer is formed in direct contact with the high voltage device area.

12 . The method as defined in claim 1 , wherein the first gate-insulating layer is oxide nitride.