Pulse generating circuit and UWB communication system
A pulse generating circuit includes a starting circuit which generates m (two or larger integer) starting signals at predetermined time intervals based on a generation starting signal, and m pulse wave generating sub circuits which have the same characteristics and generate pulse waves having pulse width Pw for n cycles (n: 1 or larger integer) based on the respective m starting signals.
1. A pulse generating circuit, comprising:
a starting circuit which generates m starting signals at predetermined time intervals based on a generation starting signal, wherein m is an integer greater than or equal to two; and
m pulse wave generating sub circuits which have the same characteristics and generate pulse waves having pulse width Pw for n cycles based on the respective m starting signals, wherein n is an integer greater than or equal to one,
wherein the m pulse wave generating sub circuits include a plurality of inverter delay circuits each delay of which is set at the pulse width Pw, and a pulse wave generating logic circuit which generates the pulse waves based on output signals from the plural inverter delay circuits.
2. The pulse generating circuit according to claim 1 , wherein:
m is equal to two; and
each of the pulse wave generating sub circuits generates the pulse waves based on the corresponding one of the m starting signals generated from the starting circuit which sets the predetermined time interval at the pulse width Pw.
3. The pulse generating circuit according to claim 2 , further comprising a cross-coupled inverter connected between output nodes where the phases of the outputs from the inverter delay circuits contained in the pulse wave generating sub circuits are reversed in a predetermined pair of the m pulse wave generating sub circuits.
4. The pulse generating circuit according to claim 1 , wherein:
m is equal to two; and
each of the pulse wave generating sub circuits generates the pulse waves based on the corresponding one of the m starting signals generated from the starting circuit which sets the predetermined time interval at the pulse width Pw/2.
5. The pulse generating circuit according to claim 4 , further comprising an adding and subtracting circuit which achieves addition and subtraction of the pulse waves generated from the respective pulse wave generating sub circuits.
6. The pulse generating circuit according to claim 1 , wherein:
m is equal to four; and
each of the pulse wave generating sub circuits generates the pulse waves based on the corresponding one of the m starting signals generated from the starting circuit which sets the predetermined time interval at the pulse width Pw/2.
7. The pulse generating circuit according to claim 1 , wherein the starting circuit includes a bi-phase signal generating circuit for generating signals of two phases which simultaneously rise and fall based on the generation starting signal, and the inverter delay circuit connected to one of output signals from the bi-phase signal generating circuit.
8. The pulse generating circuit according to claim 1 , wherein the starting circuit includes a first delay circuit producing delay set at the pulse width Pw and a second delay circuit producing delay set at a value equivalent to the pulse width Pw×1.5.
9. The pulse generating circuit according to claim 1 , further comprising a starting signal selecting circuit which selects one pulse wave generating sub circuit which receives the m starting signals generated from the starting circuit from the m pulse wave generating sub circuits based on transmitted data.
10. The pulse generating circuit according to claim 1 , further comprising an output selecting circuit which selects one pulse wave output target which receives the pulse waves generated from the m pulse wave generating sub circuits from pulse wave output targets based on transmitted data.
11. An ultra-wideband (UWB) communication system, comprising the pulse generating circuit according to claim 1 .
12. The pulse generating circuit according to claim 1 , wherein the pulse width of the generation starting signal inputted to the starting circuit is equal to and larger than the pulse width Pw and smaller than a value equivalent to Pw×4×n.
13. The pulse generating circuit according to claim 1 , wherein the cycle of the generation starting signal inputted to the starting circuit is a cycle equivalent to a value an even number times larger than the pulse width Pw.
14. The pulse generating circuit according to claim 1 , wherein the inverter delay circuits control delay of the inverter delay circuits based on an outside control signal.