SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit device is provided. The operating frequency generating component generates an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates. The extracting component extracts a critical path that is the slowest path when a data signal propagates between predetermined terminals inside the semiconductor integrated circuit. The instruction prefetch executing component prefetches an instruction relating to the critical path that has been extracted by the extracting component. The processing configuration changing component changes the processing configuration so as to realize transmission of the data signal within a predetermined cycle of the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.
1 . A semiconductor integrated circuit device comprising:
an operating frequency generating component that generates an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates;
an extracting component that extracts a critical path that is the slowest path when a data signal propagates between predetermined terminals inside the semiconductor integrated circuit;
an instruction prefetch executing component that prefetches an instruction relating to the critical path that has been extracted by the extracting component; and
a processing configuration changing component that changes the processing configuration so as to realize transmission of the data signal within a predetermined cycle of the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.
2 . The semiconductor integrated circuit device of claim 1 , wherein the processing configuration changing component realizes completion of transmission of the data signal within the predetermined cycle of the operating frequency by regulating the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.
3 . The semiconductor integrated circuit device of claim 1 , wherein the processing configuration changing component realizes completion of transmission of the data signal within the predetermined cycle of the operating frequency by regulating a signal strength level correlated with the rise time of signal propagation using the instruction prefetch executing component when the data signal passes through the path of the critical path.
4 . The semiconductor integrated circuit device of claim 3 , wherein the signal strength level is increase and decrease of a voltage.
5 . The semiconductor integrated circuit device of claim 1 , wherein the predetermined cycle is one cycle.
6 . A critical path control method in a semiconductor integrated circuit device comprising:
(a) generating an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates;
(b) extracting a critical path that is the slowest path when a data signal propagates between predetermined terminals inside the semiconductor integrated circuit;
(c) prefetching, with an instruction prefetch executing component, an instruction relating to the critical path that has been extracted; and
(d) changing the processing configuration so as to realize transmission of the data signal within a predetermined cycle of the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.
7 . The critical path control method of claim 6 , wherein the method realizes completion of transmission of the data signal within the predetermined cycle of the operating frequency by regulating the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.
8 . The critical path control method of claim 6 , wherein the method realizes completion of transmission of the data signal within the predetermined cycle of the operating frequency by regulating a signal strength level correlated with the rise time of signal propagation using the instruction prefetch executing component when the data signal passes through the path of the critical path.
9 . The critical path control method of claim 8 , wherein the signal strength level is increase and decrease of a voltage.
10 . The critical path control method of claim 8 , wherein the predetermined cycle is one cycle.