Semiconductor device including an embedded contact plug
View Patent ↗A semiconductor device includes an active area isolated by an isolation area on a semiconductor substrate. A transistor includes a gate electrode extending across the active area, source/drain regions formed in the active area on both sides of the gate electrode, and impurity-containing contact plugs connected to the source/drain regions. The source/drain regions are formed by thermal diffusion of impurities from the impurity-containing contact plugs toward the active area.
1. A semiconductor device comprising:
a semiconductor substrate including an active area isolated by an isolation area;
a gate electrode extending across said active area;
source and drain regions disposed in said active area in association with said gate electrode, including an impurity-containing conductive plug embedded therein; and
a vertical layer area disposed between said active area and said isolation area, comprising electrode portions connected to said gate electrode and isolation portions adjacent to a sidewall of said electrode portions, wherein
said electrode portions flank said active area at an intersection of said active area and said gate electrode, such that the top and side surfaces of said active area at said intersection are covered by said gate electrode and said electrode portions, respectively, and
said isolation portions flanks said active area at said source and drain regions.
2. The semiconductor device according to claim 1 , wherein said electrode portions configure a channel extending between said source region drain regions.
3. The semiconductor device according to claim 1 , wherein said impurity-containing conductive plug is formed in self-alignment with a sidewall insulation film formed on a sidewall of said gate electrode.
4. A semiconductor device comprising:
a semiconductor substrate including an active area isolated by an isolation area:
a gate electrode extending across said active area; and
source and drain regions disposed in said active area in association with said gate electrode, wherein
each of said source and drain regions comprises an impurity-containing conductive plug embedded therein,
a vertical layer area is provided between said active area and said isolation area,
said active area and said vertical layer area extend in a first direction, and said gate electrode extends in a second direction intersecting said first direction,
said vertical layer area includes a first vertical layer area portion filled with a conductive material configuring a portion of said gate electrode, and a second vertical layer area portion filled with an insulation material and disposed adjacent to said first vertical layer area portion and said source and drain regions, and
said source and drain regions each have a bottom located above a bottom of said vertical layer area.
5. The semiconductor device according to claim 1 , wherein said impurity-containing conductive plug is connected to an interconnection overlying said semiconductor substrate.
6. The semiconductor device according to claim 1 , wherein said impurity-containing conductive plug has a substantially square bottom.
7. A DRAM device including a semiconductor device according to claim 1 .
8. A data processing system including the DRAM device according to claim 7 .