Internal memory for transistor outline packages
View Patent ↗A transistor outline (TO) package includes a housing having a window and a substrate. Circuitry is coupled to the substrate within the housing. The circuitry comprises a laser diode and memory configured to store information related to the TO package. Electrical connectors are coupled to the substrate at the opposite side to the circuitry. At least one of the electrical connectors is electrically connected to the memory. A disclosed method includes assembling a TO package, testing the TO package, storing results of the testing in memory, and making the information stored in the memory, including the results of the testing, available to a device external to the TO package. The TO package includes a laser diode and memory configured to store information related to the TO package.
1. A device comprising:
a transistor outline (TO) package including:
a housing having a window;
a substrate;
circuitry coupled to the substrate within the housing, the circuitry comprising a laser diode and memory storing information related to the TO package; and
electrical connectors coupled to the substrate and electrically connected to the memory;
wherein the TO package is configured to be embedded in a transmitter optical subassembly.
2. The device of claim 1 , wherein the TO package is a sealed transistor outline (TO) can.
3. The device of claim 1 , wherein the circuitry includes an amplifier.
4. The device of claim 3 , wherein the memory and the amplifier are provided within a common integrated circuit.
5. The device of claim 1 , wherein the substrate is a headerboard and the circuitry is configured to be electrically coupled to a ground and at least one power source.
6. The device of claim 5 , wherein the ground is a common ground.
7. The device of claim 1 , wherein at least one of the electrical connectors electrically connected to the memory is a pogo pin.
8. The device of claim 1 , wherein the information related to the TO package includes one or more of:
a slope efficiency of the laser diode;
an operating current of the laser diode for a given monitoring current;
a threshold current for the laser diode;
a serial number for the laser diode;
data corresponding to a light-current (LI) curve for the laser diode;
a light-current curve for the laser diode at monitoring temperature (IMON);
data generated by testing a performance of the TO package at different temperatures; and
spectral properties of the laser diode.
9. The device of claim 1 , wherein the memory is non-volatile memory.
10. The device of claim 1 , wherein the memory is an EEPROM.
11. The device of claim 1 , wherein the memory is configured to transmit the information to a device external to the TO package.
12. The device of claim 1 , wherein the memory is configured to be read by an external device via at least one electrical connector electrically coupled to the memory.
13. The device of claim 1 , wherein at least one of the electrical connectors electrically connected to the memory includes a component that is configured to sever the electrical connection to the memory in response to a predefined input.
14. The device of claim 1 , wherein the information related to the TO package is accessible prior to manufacturing of a respective transmitter optical subassembly that includes the TO package as a component but is inaccessible after manufacturing of the respective transmitter optical subassembly has been completed.
15. The device of claim 1 , wherein the information related to the TO package stored in the memory includes information related to properties of the TO package before it is integrated into a respective transmitter optical subassembly.
16. A transistor outline (TO) package comprising:
a substrate having a first side and a second side;
multiple electrical connectors coupled to the first side of the substrate;
circuitry coupled to the second side of the substrate, wherein the circuitry comprises:
a laser diode; and
a memory storing information related to the TO package; and
a housing at least partially enclosing the circuitry,
wherein at least one of the electrical connectors is electrically coupled to the memory; and
wherein the TO package is configured to be embedded in a transmitter optical subassembly.
17. The TO package of claim 16 , wherein the TO package is a sealed transistor outline (TO) can.
18. The TO package of claim 16 , wherein the circuitry includes an amplifier.
19. The TO package of claim 18 , wherein the memory and the amplifier are provided within a common integrated circuit.
20. The TO package of claim 16 , wherein the information related to the TO package is accessible prior to manufacturing of a respective transmitter optical subassembly that includes the TO package as a component but is inaccessible after manufacturing of the respective transmitter optical subassembly has been completed.