Methods and apparatus for processing variable length coded data
View Patent ↗An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.
1. A method of handling coefficient data received from a first memory, said method comprising:
receiving a coefficient value stored in said first memory at a given address;
receiving an index register value stored in an index register at an address corresponding to said given address;
determining, based on said index register value, whether to write said coefficient value to a second memory;
receiving a read command specifying an address in said second memory;
determining an address in said first memory based on said address in said second memory; and
providing said address in said first memory to said first memory.
2. The method of claim 1 further comprising determining, based on said index register value, whether to write a predetermined default value to said second memory.
3. The method of claim 2 wherein said predetermined default value is a null value.
4. A direct memory access apparatus operable to:
receive a coefficient value stored in a first memory at a given address;
receive an index register value stored in an index register at an address corresponding to said given address;
determine, based on said index register value, whether to write said coefficient value to a second memory;
receive a read command specifying an address in said second memory;
determine an address in said first memory based on said address in said second memory; and
provide said address in said first memory to said first memory.
5. The direct memory access apparatus of claim 4 , further operable to determine, based on said index register value, whether to write a predetermined default value to said second memory.
6. The direct memory access apparatus of claim 5 wherein said predetermined default value is a null value.