Moving hardware context structures in memory while maintaining system operation

1. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor;

a first block of the memory that contains hardware context information;

a hardware adapter external to the memory and coupled to the at least one processor, the hardware adapter supporting a plurality of virtual connections that each have corresponding hardware context information stored in the first block of the memory, the hardware adapter reading the hardware context information for the plurality of virtual connections from the first block of the memory and writing the hardware context information for the plurality of virtual connections to a second block of the memory without shutting down the plurality of virtual connections.

2. The apparatus of claim 1 wherein the hardware adapter comprises:

a first register;

a second register;

a dividing line selector register that contains a context entry number; and

a local context table that contains a portion of the hardware context information in the first block of memory.

3. The apparatus of claim 2 wherein the local context table includes a pin bit for each context entry in the local context table, wherein a setting of a pin bit causes the corresponding context entry to be retrieved from the memory into the local context table, and wherein the hardware adapter keeps the corresponding context entry in the local context table as long as the pin bit is set.

4. The apparatus of claim 3 wherein a clearing of a pin bit allows the hardware adapter to write the corresponding context entry to the memory.

5. The apparatus of claim 4 wherein the hardware adapter accesses a block of memory with a beginning address specified in the first register when a desired context entry has a context entry number greater than or equal to a value in the dividing line register, and accesses a block of memory with a beginning address specified in the second register when the desired context entry has a context entry number less than the value in the dividing line register.

6. The apparatus of claim 5 wherein the hardware adapter moves the hardware context information for the plurality of virtual connections in the first block of memory to the second block of memory by performing the steps of:

(A) writing the starting address of the second block of memory to the second register;

(B) setting a pin bit in the local context table for a plurality of entries in the first block of memory;

(C) reading the plurality of entries from the first block of memory into the local context table;

(D) incrementing the dividing line selector by the number of the plurality of entries read in step (C); and

(E) clearing the pin bit in each of the plurality of entries read in step (C), thereby causing each of the plurality of entries to be automatically written to the second block of memory when each of the plurality of entries is cast out of the local context table.

7. The apparatus of claim 2 wherein the hardware adapter accesses a block of memory with a beginning address specified in the first register when a desired context entry has a context entry number greater than or equal to a value in the dividing line register, and accesses a block of memory with a beginning address specified in the second register when the desired context entry has a context entry number less than the value in the dividing line register.

8. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor;

a first block of the memory that contains hardware context information;

a hardware adapter external to the memory and coupled to the at least one processor, the hardware adapter supporting a plurality of virtual connections that each have corresponding hardware context information stored in the first block of the memory, the hardware adapter comprising:

a first register;

a second register;

a dividing line selector register that contains a context entry number; and

a local context table that contains a portion of the hardware context information in the first block of memory, wherein the local context table includes a pin bit for each context entry, wherein a setting of a pin bit causes the corresponding context entry to be retrieved from the memory into the local context table;

wherein the hardware adapter keeps a context entry in the local context table as long as the corresponding pin bit is set, and wherein a clearing of a pin bit allows the hardware adapter to cast out the corresponding context entry to the memory, wherein the hardware adapter accesses a block of memory with a beginning address specified in the first register when a desired context entry has a context entry number greater than or equal to a value in the dividing line register, and accesses a block of memory with a beginning address specified in the second register when the desired context entry has a context entry number less than the value in the dividing line register, wherein the hardware adapter moves the hardware context information for the plurality of virtual connections in the first block of memory to the second block of memory without shutting down the plurality of virtual connections by performing the steps of:

(A) writing the staffing address of a second block of the memory to the second register;

(B) setting a pin bit in the local context table for a plurality of entries in the first block of memory;

(C) reading the plurality of entries from the first block of memory into the local context table;

(D) incrementing the dividing line selector by the number of the plurality of entries read in step (C); and

(E) clearing the pin bit in each of the plurality of entries read in step (C), thereby causing each of the plurality of entries to be automatically written to the second block of memory when each of the plurality of entries is cast out of the local context table.

9. The apparatus of claim 8 wherein the plurality of entries read in step (C) comprises a number of entries that is contained within a single page of memory.

10. The apparatus of claim 9 wherein the hardware adapter repeats steps (B)-(E) for each of N pages of memory, where N equals a number of memory pages in the second block of the memory.

11. A program product comprising:

(A) adapter logic for a hardware adapter external to a memory that supports a plurality of virtual connections that each have corresponding hardware context information stored in a first block of the memory, the adapter logic reading hardware context information for the plurality of virtual connections from the first block of memory and writing the hardware context information for the plurality of virtual connections to a second block of memory without shutting down the plurality of virtual connections; and

(B) computer-readable recordable media bearing the adapter logic.

12. The program product of claim 11 wherein the adapter logic accesses:

a first register;

a second register;

a dividing line selector register that contains a context entry number; and

a local context table that contains a portion of the hardware context information in the first block of memory.

13. The program product of claim 12 wherein the local context table includes a pin bit for each context entry in the local context table, wherein a setting of a pin bit causes the corresponding context entry to be retrieved from the memory into the local context table, and wherein the adapter logic keeps the corresponding context entry in the local context table as long as the pin bit is set.

14. The program product of claim 13 wherein a clearing of a pin bit allows the adapter logic to write the corresponding context entry to the memory.

15. The program product of claim 14 wherein the adapter logic accesses a block of memory with a beginning address specified in the first register when a desired context entry has a context entry number greater than or equal to a value in the dividing line register, and accesses a block of memory with a beginning address specified in the second register when the desired context entry has a context entry number less than the value in the dividing line register.

16. The program product of claim 15 wherein the adapter logic moves the hardware context information for the plurality of virtual connections in the first block of memory to the second block of memory by performing the steps of:

(A) writing the starting address of the second block of memory to the second register;

(B) setting a pin bit in the local context table for a plurality of entries in the first block of memory;

(C) reading the plurality of entries from the first block of memory into the local context table;

(D) incrementing the dividing line selector; and

(E) clearing the pin bit in each of the plurality of entries read in step (C), thereby causing each of the plurality of entries to be automatically written to the second block of memory when each of the plurality of entries is cast out of the local context table.

17. The program product of claim 12 wherein the adapter logic accesses a block of memory with a beginning address specified in the first register when a desired context entry has a context entry number greater than or equal to a value in the dividing line register, and accesses a block of memory with a beginning address specified in the second register when the desired context entry has a context entry number less than the value in the dividing line register.

18. A program product comprising:

(A) adapter logic for a hardware adapter supporting a plurality of virtual connections that each have corresponding hardware context information stored in a first block of memory, the adapter logic comprising:

logic for using a local context table that contains a portion of the hardware context information in the first block of memory, wherein the local context table includes a pin bit for each context entry, wherein a setting of a pin bit causes a corresponding context entry to be retrieved from the first block of memory into the local context table;

wherein the adapter logic keeps a context entry in the local context table as long as the corresponding pin bit is set, and wherein a clearing of a pin bit allows the adapter logic to cast out the corresponding context entry to the memory, wherein the adapter logic accesses a block of memory with a beginning address specified in a first register when a desired context entry has a context entry number greater than or equal to a value in a dividing line register, and accesses a block of memory with a beginning address specified in a second register when the desired context entry has a context entry number less than the value in the dividing line register, wherein the adapter logic moves the hardware context information for the plurality of virtual connections in the first block of memory to a second block of memory without shutting down the plurality of virtual connections by performing the steps of:

(A1) writing the staffing address of the second block of memory to the second register;

(A2) setting a pin bit in the local context table for a plurality of entries in the first block of memory;

(A3) reading the plurality of entries from the first block of memory into the local context table;

(A4) incrementing the dividing line selector register by the number of the plurality of entries read in step (A3); and

(A5) clearing the pin bit in each of the plurality of entries read in step (A3), thereby causing each of the plurality of entries to be automatically written to the second block of memory when each of the plurality of entries is cast out of the local context table; and

(B) computer-readable recordable media bearing the adapter logic.

19. The program product of claim 18 wherein the plurality of entries read in step (C) comprises a number of entries that is contained within a single page of memory.

20. The program product of claim 19 wherein the adapter logic repeats steps (B)-(E) for each of N pages of memory, where N equals a number of memory pages in the second memory block.