Systems and methods for pipelined analog to digital conversion
View Patent ↗Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.
1. A pipelined analog to digital converter circuit, the circuit comprising:
a first comparator, wherein the first comparator is operable to compare an analog input to a first voltage reference upon assertion of the first clock;
a second comparator, wherein the second comparator is operable to compare the analog input to a second voltage reference upon assertion of the second clock;
a multiplexer tree, wherein the multiplexer tree includes at least a first tier multiplexer and a second tier multiplexer, wherein the first tier multiplexer receives an output of the first comparator and an output of the second comparator, wherein the second tier multiplexer receives an output derived from the first tier multiplexer, and wherein the second tier multiplexer provides an output bit;
a bit enable set, wherein the bit enable set receives the output bit; and
wherein the bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer.
2. The circuit of claim 1 , wherein the bit enable set is used to gate at least one of the first clock and the second clock.
3. The circuit of claim 1 , wherein the first clock and the second clock are the same clock, and wherein the first comparator and the second comparator are enabled on all bit periods.
4. The circuit of claim 1 , wherein the first reference voltage and the second reference voltage are programmable.
5. The circuit of claim 1 , wherein the bit enable set is received from individual flip-flop outputs of a shift register, and wherein an initial flip-flop in the shift register receives the output bit.
6. The circuit of claim 1 , wherein an output of the first tier multiplexer is registered to generate a registered value, and wherein the output derived from the first tier multiplexer is derived from the registered value.
7. The circuit of claim 6 , wherein the bit enable set includes a first bit enable and a second bit enable, and wherein the first bit enable is provided as a selector input to the first tier multiplexer, and wherein the second bit enable is provided as a selector input to the second tier multiplexer.
8. The circuit of claim 7 , wherein both the first bit enable and the second bit enable are used to gate both the first clock and the second clock.
9. The circuit of claim 8 , wherein the first comparator and the second comparator are two of a number of comparators, wherein the first clock and the second clock are derived from an input clock, and wherein only one half of the number of comparators are enabled on any given cycle of the input clock.
10. The circuit of claim 8 , wherein the first comparator and the second comparator are two of a number of comparators, wherein the first clock and the second clock are derived from an input clock, and wherein only one quarter of the number of comparators are enabled on any given cycle of the input clock.
11. The circuit of claim 8 , wherein the first comparator and the second comparator are two of a number of comparators, wherein the first clock and the second clock are derived from an input clock, and wherein less than one quarter of the number of comparators are enabled on any given cycle of the input clock.
12. The circuit of claim 1 , wherein the first tier multiplexer is a first multi-tier multiplexer, and wherein the second tier multiplexer is a second multi-tier multiplexer.
13. A communication system, the system comprising:
a receiver including an analog to digital converter, wherein the analog to digital converter includes:
a first comparator, wherein the first comparator is operable to compare an analog input to a first voltage reference upon assertion of the first clock;
a second comparator, wherein the second comparator is operable to compare the analog input to a second voltage reference upon assertion of the second clock;
a multiplexer tree, wherein the multiplexer tree includes at least a first tier multiplexer and a second tier multiplexer, wherein the first tier multiplexer receives an output of the first comparator and an output of the second comparator, wherein the second tier multiplexer receives an output derived from the first tier multiplexer, and wherein the second tier multiplexer provides an output bit;
a bit enable set, wherein the bit enable set receives the output bit; and
wherein the bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer.
14. The communication system of claim 13 , wherein the communication system further includes a transmitter, and wherein the transmitter transmits information to the receiver via a medium.
15. The communication system of claim 14 , wherein the communication system is a hard disk drive system, and wherein the medium is a storage medium.
16. The communication system of claim 14 , wherein the communication system is a wireless communication system, and wherein the medium is a wireless medium.
17. A method for analog to digital conversion, the method comprising:
providing a plurality of comparators, wherein each of the plurality of comparators receives an analog input signal and a respective reference voltage;
receiving the analog input signal;
selecting an output bit of a respective one of the plurality of comparators using a synchronized multiplexer tree, wherein the synchronized multiplexer tree includes at least a first tier multiplexer and a second tier multiplexer, wherein the first tier multiplexer receives outputs from each of the plurality of comparators, wherein a register receives outputs from the first tier multiplexer, wherein the second tier multiplexer receives an output derived from the register, and wherein the second tier multiplexer provides the output bit for a current bit period; and
selecting the output bit based at least in part on the output bit from a preceding bit period.
18. The method of claim 17 , wherein the output bit from the preceding bit period is used to enable a subset of the plurality of comparators.
19. The method of claim 18 , wherein the subset of the plurality of comparators is selected from a group consisting of: one half of the subset of comparators, one quarter of the subset of comparators, and less than one quarter of the subset of comparators.
20. The method of claim 17 , wherein the first tier multiplexer is a first multi-tier multiplexer, and wherein the second tier multiplexer is a second multi-tier multiplexer.