Apparatus and method for processing wirelessly communicated data and clock information within an electronic device

1. An electronic device ( 12 ) for processing information that includes data and clock information and that is wirelessly received from another electronic device ( 14 ), the electronic device ( 12 ) comprising:

a first processor ( 18 ) that controls operations associated only with wireless communications with the another electronic device ( 14 ) and excluding operations associated only with the electronic device ( 12 ), the information wirelessly received by the electronic device from the another electronic device comprising at least one information packet containing the data and clock information, a preamble that precedes the at least one information packet and a start command that follows the preamble and that precedes the at least one information packet, the first processor ( 18 ) configured to extract the preamble, the start command and the at least one information packet from the information wirelessly received by the electronic device ( 12 ) from the another electronic device ( 14 ),

a second processor ( 16 ) that controls the operations associated only with the electronic device ( 12 ) and excluding the operations associated with the wireless communications with the another device ( 14 ),

a phase lock loop circuit ( 56 ) having an input connected to the first processor ( 18 ) a first output connected to the second processor ( 16 ) and a second output, the phase lock loop circuit ( 56 ) being normally in a sleep state and configured to be responsive to the preamble to wake up from the sleep state and to lock and run with a phase lock loop clock that operates at a phase lock loop clock rate, wherein the phase lock loop circuit ( 56 ) extracts the clock information from the at least one information packet and produces the clock signal and

a decoder circuit ( 58 ) having a first input connected to the first processor ( 18 ), a second input connected to the phase lock loop circuit ( 56 ) and an output connected to the second processor ( 16 ), wherein the decoder circuit ( 58 ) decodes the data from the at least one information packet and produces the data, the decoder circuit ( 58 ) decodes the start command by removing the clock information from the extracted start command as a function of the phase lock loop clock,

and wherein the decoded start command received by the second processor ( 16 ) alerts the second processor ( 16 ) that data will subsequently be sent thereto by the another electronic device ( 14 )

wherein the second processor ( 16 ) synchronously receives the data using the clock signal,

and wherein only the second processor ( 16 ) acts upon the data.

2. The electronic device ( 12 ) of claim 1 wherein the phase lock loop circuit ( 56 ) is configured to be responsive to transitions of the data contained in the extracted start command to update operation of the phase lock loop circuit ( 56 ).

3. The electronic device ( 12 ) of claim 1 wherein the decoder circuit ( 58 ) is configured to decode the data from the at least one information packet by removing the clock information from the at least one information packet as a function of the phase lock loop clock.

4. The electronic device ( 12 ) of claim 3 wherein the phase lock loop circuit ( 56 ) is configured to be responsive to transitions of the data contained in the at least one information packet to update operation of the phase lock loop circuit ( 56 ).

5. The electronic device ( 12 ) of claim 3 wherein the information wirelessly received by the electronic device ( 12 ) from the another electronic device ( 14 ) comprises a plurality of information packets following the start command,

and wherein the decoder circuit ( 58 ) is configured to decode the data from the plurality of information packets by removing the clock information from each of the plurality of information packet as a function of the phase lock loop clock.

6. The electronic device ( 12 ) of claim 5 wherein the phase lock loop circuit ( 56 ) is configured to be responsive to transitions of the data contained in the each of the plurality of information packets to update operation of the phase lock loop circuit ( 56 ).

7. The electronic device ( 12 ) of claim 1 wherein the information wirelessly received by the electronic device ( 12 ) from the another electronic device ( 14 ) further comprises a stop command that follows the at least one information packet,

and wherein the first processor ( 18 ) is configured to extract the stop command from the information wirelessly received by the electronic device ( 12 ) from the another electronic device ( 14 ),

and wherein the decoder circuit ( 58 ) decodes the stop command by removing the clock information from the information extracted stop command as a function of the phase lock loop clock,

and wherein the decoded stop command received by the second processor ( 16 ) alerts the second processor ( 16 ) that no further data will subsequently be sent thereto by the another electronic device ( 14 ).

8. The electronic device ( 12 ) of claim 7 wherein the phase lock loop circuit ( 56 ) is configured to be responsive to transitions of the data contained in the extracted stop command to update operation of the phase lock loop circuit ( 56 ).

9. The electronic device ( 12 ) of claim 7 wherein the phase lock loop circuit ( 56 ) reenters the sleep state resulting from failure by the electronic device ( 12 ) to wirelessly receive further information from the another electronic device ( 14 ) following receipt of the stop command.