Devices, systems, and methods regarding programmable logic controller communications
Certain exemplary embodiments can provide a system, which can comprise a signal interface that is adapted to transmit a signal between a programmable logic controller and an Input/Output (I/O) module. The programmable logic controller can be communicatively coupled to the I/O module via an opto-coupler, which can be adapted to electrically isolate the programmable logic controller from the I/O module.
1. A system comprising:
a signal interface circuit including circuitry for integrating a control sub-signal within a clock sub-signal, wherein the signal interface circuit:
forms an integrated signal comprising the clock sub-signal and the control sub-signal; and
transmits the integrated signal between a programmable logic controller and an Input/Output (I/O) module, said programmable logic controller communicatively coupled to said I/O module via a single opto-coupler,
wherein said clock sub-signal provides temporal information regarding said integrated signal,
wherein said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.
2. The system of claim 1 , further comprising:
said I/O module.
3. The system of claim 1 , further comprising:
said opto-coupler.
4. The system of claim 1 , further comprising:
said programmable logic controller.
5. The system of claim 1 , wherein:
said signal interface circuit recovers an incoming clock sub-signal from an incoming signal that comprises said incoming clock sub-signal integrated with an incoming control sub-signal.
6. The system of claim 1 , wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic, and
said combinatorial logic integrates said clock sub-signal and said control sub-signal to form said integrated signal.
7. The system of claim 1 , wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic, and
said combinatorial logic integrates said clock sub-signal, said control sub-signal, and a data sub-signal to form said integrated signal.
8. The system of claim 1 , wherein:
said signal interface circuit comprises a counter that provides said clock sub-signal to combinatorial logic,
said combinatorial logic integrates said clock sub-signal and said control sub-signal to form said integrated signal, and
said combinatorial logic provides an initiation signal that resets said counter at an end of said integrated signal.
9. The system of claim 1 , wherein:
said signal interface circuit comprises a pulse high detector.
10. The system of claim 1 , wherein:
said signal interface circuit comprises a pulse high detector that recovers said control sub-signal from said integrated signal.
11. The system of claim 1 , wherein:
said signal interface circuit comprises a pulse low detector that recovers said control sub-signal from said integrated signal.
12. The system of claim 1 , wherein:
said integrated signal comprises a data sub-signal, said data sub-signal comprising information from said register transfer.
13. A method comprising:
integrating a control sub-signal within a clock sub-signal using a signal interface circuit including circuitry forming an integrated signal, the integrated signal including the clock sub-signal and the control sub-signal; and
causing the integrated signal to be transmitted between a programmable logic controller and an Input/Output (I/O) module via the signal interface circuit, said programmable logic controller using said integrated signal to control a process, said programmable logic controller communicatively coupled to said I/O module via an opto-coupler,
wherein:
said clock sub-signal provides temporal information regarding said integrated signal,
said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit receiving said integrated signal recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.
14. The method of claim 13 , further comprising:
recovering said control sub-signal from said integrated signal.
15. The method of claim 13 , further comprising:
via a pulse high detector, recovering said control sub-signal from said integrated signal.
16. The method of claim 13 , further comprising:
via a pulse low detector, recovering said control sub-signal from said integrated signal.
17. The method of claim 13 , further comprising:
transmitting said integrated signal.
18. The method of claim 13 , further comprising:
integrating said control sub-signal into said integrated signal.
19. The method of claim 13 , further comprising:
via a combinatorial logic circuit, integrating said control sub-signal into said integrated signal.
20. The method of claim 13 , further comprising:
automatically resetting a counter of said signal interface circuit responsive to an end of said integrated signal.
21. A non-transitory machine-readable medium comprising machine-implementable instructions for activities comprising:
integrating a control sub-signal within a clock sub-signal using a signal interface circuit including circuitry forming an integrated signal, the integrated signal comprising a clock sub-signal and a control sub-signal; and
causing the integrated signal to be transmitted between a programmable logic controller and an Input/Output (I/O) module via the signal interface circuit, said programmable logic controller using said integrated signal to control a process, said programmable logic controller communicatively coupled to said I/O module via an opto-coupler,
wherein:
said clock sub-signal provides temporal information regarding said integrated signal,
said control sub-signal comprises a framing signal indicative of a completion of a register transfer, and
a circuit receiving said integrated signal recovers said clock sub-signal and said control sub-signal from said integrated signal, wherein the control sub-signal is recovered via said circuit detecting said control sub-signal by differentiating short length pulses from pulses that have a longer length.