IP Library Granted Patent US 8,041,546
Granted Patent B2
US 8,041,546 · App. 12/137,257 · Granted Oct 18, 2011

Capacitance modeling

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Quick Facts
Patent No.
US 8,041,546
App. No.
12/137,257
Granted
Oct 18, 2011
Kind
B2
Abstract

A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (ε 1 ) and the substrate is a second dielectric with a second permittivity (ε 2 ). The method models the capacitance (C 1 ) for values of the first and second permittivity (ε 1 , ε 2 ) based on known capacitance (C 2 ) computed for a basis structure with the same first permittivity (ε 1 ) and a different second permittivity (ε 2 ). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C 1 ) through one or more known capacitances (C 2 ).

Claims (59)

1. A method of modeling capacitance for a subject structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate, wherein the capacitance of the conductors is a function of current frequency, wherein the method includes the steps of:

characterizing the surrounding dielectric material as a first dielectric with a first permittivity (ε 1 ) and the substrate as a second dielectric with a second permittivity (ε 2 );

determining a reflection coefficient for the subject structure and a basis structure based on the first and second permittivities (ε 1 , ε 2 );

determining a minor capacitance for the basis structure; and

computing a capacitance of the subject structure based on the reflection coefficients and the mirror capacitance.

2. A method as claimed in claim 1 , wherein the minor capacitance is computed using a charge density function of the basis structure.

3. A method as claimed in claim 1 , wherein the mirror capacitance is an averaged mirror capacitance based on a uniform charge density approximation for the basis structure.

4. A method as claimed in claim 1 , wherein the method includes the following steps:

defining:

C 1 as the capacitance for the subject structure;

C 2 as the capacitance for the basis structure;

ε 21 as the substrate permittivity ε 2 of the subject structure; and

ε 22 as the substrate permittivity ε 2 of the basis structure;

determining the reflection coefficient, k i =(ε 1 −ε 2i )/(ε 1 +ε 2i ) for i=1,2;

determining if a charge density function σ(X,k 2 ) for a basis solution is available, if it is available, computing the mirror capacitance C*(k 2 )=C*(X 1 ,X 2 ,k 2 ) which is fully defined by σ(X,k 2 ), and if the charge density function for the basis solution is not available, computing the averaged mirror capacitance C*(k 2 )=C* avg (k 2 ) based on the uniform charge density approximation; and

computing the capacitance C 1 using an extrapolation formula:

C 1 =1/(1 /C 2 +( k 1 −k 2 )/ C *( k 2 )).

5. The method as claimed in claim 1 , wherein the surrounding dielectric material is an insulating material and the substrate behaves as a conductor at low frequencies and as a dielectric at very high frequencies.

6. The method as claimed in claim 1 , wherein the dielectric is an oxide dielectric and the substrate is a silicon substrate.

7. The method as claimed in claim 1 , wherein the pair of long conductors each have a width and metal layer thickness of the same order.

8. The method as claimed in claim 1 , wherein the pair of long conductors are spaced apart by a distance of the same order as the width and thickness of the conductors.

9. The method as claimed in claim 1 , wherein the cross-section of each of the long conductors is constant along the length.

10. The method as claimed in claim 1 , wherein each of the long conductors is formed of a single conductor or more than one parallel conductor.

11. An integrated circuit design system for modeling a capacitance for a subject structure comprising a pair of long conductors surrounded by a dielectric material and supported by substrate, the surrounding dielectric material is a first dielectric with a first permittivity (ε 1 ) and the substrate is a second dielectric with a second permittivity (ε 2 ), the system comprising:

a memory storage device; and

a processor storage device connected to the memory storage device, and adopted for performing a method comprising:

determining a reflection coefficient for the subject structure and a basis structure based on the first and second permittivities (ε 1 , ε 2 ) of the subject structure and the basis structure;

determining a mirror capacitance for the basis structure; and

computing the capacitance of the subject structure based on the reflection coefficients and the mirror capacitance.

12. The integrated circuit design system as claimed in claim 11 , said method further comprising:

determining the reflection coefficient according to k i =(ε 1 −ε 2i )/(ε 1 +ε 2i ) for i=1,2;

determining if a charge density function σ(X,k 2 ) for a basis solution is available, and if said basis solution is available, computing the “minor capacitance” C*(k 2 )=C*(X 1 ,X 2 ,k 2 ) which is fully defined by σ(X,k 2 ), and if the charge density function for the basis solution is not available, means for computing an “averaged minor capacitance” C*(k 2 )=C* avg (k 2 ) based on a uniform charge density approximation; and

computing a capacitance C 1 using an extrapolation formula:

C 1 =1/(1 /C 2 +( k 1 −k 2 )/ C *( k 2 ));

wherein

C 1 is the capacitance for the subject structure;

C 2 is the capacitance for the basis structure;

ε 21 is the substrate permittivity ε 2 of the subject structure; and

ε 22 is the substrate permittivity ε 2 of the basis structure.

13. The integrated circuit design system as claimed in claim 11 , wherein the surrounding dielectric material is an insulating material and the substrate behaves as a conductor at low frequencies and as a dielectric at very high frequencies.

14. The integrated circuit design system as claimed in claim 11 , wherein the dielectric is an oxide dielectric and the substrate is a silicon substrate.

15. The integrated circuit design system as claimed in claim 11 , wherein the pair of long conductors each have a width and metal layer thickness of the same order.

16. The integrated circuit design system as claimed in claim 11 , wherein the pair of long conductors are spaced apart by a distance of the same order as the width and thickness of the conductors.

17. The integrated circuit design system as claimed in claim 11 , wherein the cross-section of each of the long conductors is constant along the length.

18. The integrated circuit design system as claimed in claim 11 , wherein each of the long conductors is formed of a single conductor or more than one parallel conductor.

19. A computer program product stored on a computer readable storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing a method for modeling capacitance for a subject structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate, the surrounding dielectric material is a first dielectric with a first permittivity (ε 1 ) and the substrate is a second dielectric with a second permittivity (ε 2 ), said modeling method comprising:

determining a reflection coefficient for the subject structure and a basis structure based on the first and second permittivities (ε 1 , ε 2 );

determining a minor capacitance for the basis structure; and

computing a capacitance of the subject structure based on the reflection coefficients and the mirror capacitance.

20. The computer program product as claimed in claim 19 , said method further comprising:

determining the reflection coefficient, k i =(ε 1 −ε 2i )/(ε 1 +ε 2i ) for i=1,2;

determining if a charge density function σ(X,k 2 ) for the basis solution is available, if it is available, computing the “mirror capacitance” C*(k 2 )=C*(X 1 ,X 2 ,k 2 ) which is fully defined by σ(X,k 2 ), and if the charge density function for the basis solution is not available, computing an “averaged mirror capacitance” C*(k 2 )=C* avg (k 2 ) based on a uniform charge density approximation; and

computing a capacitance C 1 using an extrapolation formula:

C 1 =1/(1 /C 2 +( k 1 −k 2 )/ C *( k 2 ));

wherein

C 1 is the capacitance for the subject structure;

C 2 is the capacitance for the basis structure;

ε 21 is the substrate permittivity ε 2 of the subject structure; and

ε 22 is the substrate permittivity ε 2 of the basis structure.

Assignments (2)
CHANGE OF NAME Recorded Dec 20, 2021
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058553/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2012
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: FACEBOOK, INC.
Reel/Frame 027991/0554 →