Electronic device and method for on chip skew measurement
View Patent ↗The invention relates to an integrated electronic device for digital signal processing, which includes a phase locked loop for generating an output clock signal based on a reference clock input signal, multiple outputs for providing multiple representatives of the output clock signal, a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal, a register having multiple units each coupled by a data input to a representative of the output clock signal, and to the phase shifted output clock signal for storing single bit values in response to an edge of the shifted output clock signal, wherein the stage for generating the phase shifted output clock is controlled to selectively shift the phase of the output clock and circuitry for reading out the stored single bit values from the register is provided in order to determine the output skew of the output clock signals based on the read out single bit value.
1. An integrated electronic device for digital signal processing, comprising:
a phase locked loop for generating an output clock signal based on a reference clock input signal;
a stage for generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal and controlled to selectively shift the phase of the output clock;
a register having multiple units, each unit having a data input coupled to receive a representation of the output clock signal and a clock input coupled to receive the phase shifted output clock signal, for storing respective single bit values in response to an edge of the shifted output clock signal; and
circuitry for reading out the stored single bit values from the register as an indication of the output skew of the output clock signals.
2. The device of claim 1 , wherein the units of the register comprise flip-flops; and wherein the circuitry for reading out the stored single bit values comprises a serial bus coupled to the outputs of the respective flip-flops.
3. The device of claim 2 , further comprising buffers for generating the respective representations of the clock signal based on the output clock signal.
4. A method for determining a skew of multiple output clock signals comprising:
generating an output clock signal based on a reference clock input signal using a phase locked loop;
generating multiple representations of the output clock signal;
generating a phase shifted output clock signal having multiple phases spanning one clock period of the output clock signal;
storing the state of the value of each representation of the output clock signal in response to an edge of the shifted output clock signal; and
reading out the stored single bit values in order to determine the output skew of the representations of the output clock signal.