Methods and systems for processing of n-state symbols with XOR and EQUALITY binary functions

1. A method for processing a sequence of n-state symbols in binary form with a Linear Feedback Shift Register (LFSR), the LFSR including a plurality of outputs to provide an n-state symbol in binary form, each output enabled to provide a signal representing a bit, comprising:

performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation; and

as part of performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation, applying the LFSR for processing the sequence of n-state symbols in binary form, each n-state symbol of the sequence able to assume one of n states with n=2 p and p equal to or greater than 2 and an n-state symbol being represented by at least p bits, the LFSR implements in binary form an n-state logic function defined by an n-state truth table which determines an n-state output state of the n-state logic function as a result of a first and a second input of the n-state logic function each enabled to assume each one of n states and wherein the n-state logic function is implemented with at least one reversible binary logic function which is an EQUALITY (=) function, and

wherein application of the EQUALITY function by the LFSR in performing the processing belonging to the group consisting of scrambling, descrambling and sequence generation affects an output sequence of n-state symbols that is output by the LFSR.

2. The method of claim 1 , wherein p>2.

3. The method as claimed in claim 1 , the LFSR further comprising at least one device implementing in binary form a multiplication with a constant over GF(n=2 p ).

4. The method as claimed in claim 1 , the LFSR further comprising at least one device implementing in binary form a zero-based n-state reversible inverter in binary form.

5. The method as claimed in claim 1 , the LFSR further comprising at least one device implementing in binary form a non-zero-based n-state reversible inverter in binary form.

6. The method as claimed in claim 1 , wherein the LFSR is an LFSR in Fibonacci configuration.

7. The method as claimed in claim 1 , wherein the LFSR is an LFSR in Galois configuration.

8. The method as claimed in claim 1 , further comprising:

applying the LFSR for scrambling the sequence of n-state symbols in binary form, including the steps:

applying a second n-state logic function implemented by a plurality of binary reversible logic functions having a first and second plurality of inputs and a plurality of outputs

receiving from a source external to the LFSR a first plurality of bits representing a first n-state symbol on the first plurality of inputs of the second n-state logic function;

receiving on the second plurality of inputs of the second n-state logic function a second plurality of bits from the LFSR;

outputting on the plurality of outputs of the second n-state logic function an n-state output symbol represented by a plurality of bits;

inputting a third plurality of bits representing a third n-state symbol based on the n-state output symbol into the LFSR; and

providing on a plurality of outputs of the LFSR a sequence of scrambled n-state symbols each represented by at least p bits.

9. The method as claimed in claim 8 , further comprising connecting the plurality of outputs of the second n-state logic function to a plurality of inputs of the LFSR via an n-state reversible inverter in binary form.

10. The method as claimed in claim 8 , further comprising transforming the n-state symbol represented by at least p bits into a single n-state signal able to assume one of at least n states.

11. The method as claimed in claim 1 , wherein the LFSR is applied for generating a maximum length sequence of n-state symbols represented in binary form.

12. The method as claimed in claim 11 , wherein a correlation of the sequence with another sequence is determined by applying an n-state modified binary correlation method.

13. The method of claim 1 , wherein the n-state truth table represents a two input/single output n-state function, the truth table including n different output states.

14. The method of claim 1 , wherein the n-state function is not an addition over GF(n).

15. A system for scrambling and descrambling a sequence of k with k>2 n-state symbols each n-state symbol able to assume one of n states with n>2 and n=2 p and each symbol being represented by at least p binary signals, comprising:

a scrambler Linear Feedback Shift Register (LFSR), the LFSR enabled to process a word of at least p bits as a single n-state symbol,

wherein the scrambler scrambles a first sequence of words of at least p bits per word into a second sequence of words of at least p bits per word, and

wherein the LFSR implements in binary form an n-state logic function defined by an n-state truth table which determines an n-state output state of the n-state logic function as a result of a first and a second input of the n-state logic function each input and output enabled to assume each one of n states and wherein the n-state logic function is implemented with at least one reversible binary logic function which is an EQUALITY (=) function; and

a corresponding descrambler with a shift register in a forward connected configuration wherein the corresponding descrambler descrambles the second sequence of words into the first sequence of words.

16. The system as claimed in claim 15 , the first LFSR comprising a shift register with a plurality of register elements, each element enabled to store at least p bits.

17. The system as claimed in claim 15 , the first LFSR further comprising an n-state inverter in binary form.

18. The system as claimed in claim 15 , wherein the system is applied in a communication system using QAM-2 s modulation with s equal to or greater than 2.

19. An n-state Linear Feedback Shift Register (n-state LFSR) to provide a sequence of n-state symbols in binary form, an n-state symbol enabled to assume one of n states with n>2 and n=2 p with p>1, comprising:

at least p binary Linear Feedback Shift Registers (binary LFSRs), each binary LFSR including a binary output to provide a binary signal, the binary outputs of the at least p binary LFSRs enabled to provide a binary word representing an n-state symbol in the sequence; and

an implementation in binary form of an n-state logic function defined by a state of a first input enabled to assume any of n states, a state of a second input enabled to assume any of n states and a state of an n-state output enabled to assume any of n states, wherein an n-state truth table determines the state of the n state output as a result of the state of the first input and the state of the second input, wherein

the n-state truth table is determined only by binary reversible logic functions of which at least one is an EQUALITY (=) function, and

wherein the n-state LFSR applies the n-state logic function to provide the sequence of n-state symbols in binary form and the n-state LFSR is part of an implementation of a scrambler, a descrambler and a sequence generator.