Input sampling network that avoids undesired transient voltages
View Patent ↗Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.
1. An integrated circuit including a sampling network comprising:
a first capacitor having a first node and a second node;
a first switch transistor coupled between an input terminal and the first node of the first capacitor;
a second switch transistor coupled to the second node of the first capacitor;
a third switch transistor coupled between a reference voltage terminal and the first node of the first capacitor;
a fourth switch transistor coupled between a first bias voltage terminal and the second node of the first capacitor; and
a fifth switch transistor coupled between the first bias voltage terminal and the first node of the first capacitor.
2. The integrated circuit of claim 1 wherein the reference voltage terminal is coupled to the output of a one-bit digital-to-analog converter.
3. The integrated circuit of claim 1 wherein the reference voltage terminal is coupled to the output of a comparator.
4. The integrated circuit of claim 2 wherein the integrated circuit includes a sigma-delta modulator comprising the sampling network and the one-bit digital-to-analog converter.
5. The integrated circuit of claim 1 wherein the first switch transistor and the fourth switch transistor are closed, then later the fifth switch transistor and the second switch transistor are closed, and then later the third switch transistor and the second switch transistor are closed.
6. The integrated circuit of claim 5 wherein the first bias voltage is approximately one-half of a positive power supply voltage.
7. The integrated circuit of claim 1 wherein the second switch transistor is coupled between an integrator and the second node of the first capacitor.
8. The integrated circuit of claim 7 wherein the integrator comprises an amplifier and a second capacitor coupled between an inverting input and an output of the amplifier.
9. A method of sampling a input signal at an input signal terminal comprising:
coupling a first node of a first capacitor to the input terminal; and
coupling a second node of the first capacitor to a common-mode voltage; then
coupling the first node of the first capacitor to the common-mode voltage; and
coupling the second node of the first capacitor to an output terminal; then
coupling the first node the first capacitor to a reference voltage; and
continuing to couple the second node of the first capacitor to the output terminal.
10. The method of claim 9 wherein the reference voltage is provided by a one-bit digital-to-analog converter.
11. The method of claim 9 wherein the reference voltage is provided by a comparator.
12. The method of claim 10 wherein the integrated circuit includes a sigma-delta modulator comprising the sampling network and the one-bit digital-to-analog converter.
13. The method of claim 9 wherein the common-mode voltage is approximately one-half of a positive power supply voltage.
14. The method of claim 9 wherein the output terminal is coupled to an integrator.
15. The method of claim 14 wherein the integrator comprises an amplifier and a second capacitor coupled between an inverting input and an output of the amplifier.
16. An integrated circuit including a sampling network comprising:
a first capacitor having a first node and a second node;
a first switch to couple an input to the first node of the first capacitor;
a second switch to couple the second node of the first capacitor to an output;
a third switch to couple a reference voltage to the first node of the first capacitor;
a fourth switch to couple a first bias voltage to the second node of the first capacitor; and
a fifth switch to couple the first bias voltage to the first node of the first capacitor.
17. The integrated circuit of claim 16 wherein the reference voltage is provided by a one-bit digital-to-analog converter.
18. The integrated circuit of claim 16 wherein the reference voltage is provided by a comparator.
19. The integrated circuit of claim 16 , wherein the first switch and the fourth switch are closed, then later the fifth switch and the second switch are closed, and then later the third switch and the second switch are closed.
20. The integrated circuit of claim 19 wherein the first bias voltage is approximately one-half of a positive power supply voltage.
21. The integrated circuit of claim 16 wherein the second switch is coupled between an integrator and the second node of the first capacitor.
22. The integrated circuit of claim 21 wherein the integrator comprises an amplifier and a second capacitor coupled between an inverting input and an output of the amplifier.