CACHE ARRANGEMENT FOR GRAPHICAL APPLICATIONS
A cache arrangement for graphical applications is disclosed. One embodiment comprises receiving a first address having a first n-bit portion and corresponding to a first pixel, receiving a second address having a second n-bit portion and corresponding to the first pixel, reversing the order of the second n-bit portion to form a reversed n-bit portion, and generating a first cache entry number derived from the first n-bit portion and the reversed n-bit portion.
1 . A cache arrangement method for a graphical application, the method comprising:
receiving a first address having a first n-bit portion and corresponding to a first pixel;
receiving a second address having a second n-bit portion and corresponding to the first pixel;
reversing the order of the second n-bit portion to form a reversed n-bit portion; and
generating a first cache entry number derived from the first n-bit portion and the reversed n-bit portion.
2 . The cache arrangement method of claim 1 , wherein the first n-bit portion is the low order n-bit portion of the first address and the second n-bit portion is the low order n-bit portion of the second address.
3 . The method of claim 1 , wherein generating a first cache entry number includes performing an exclusive OR operation between a low order n-bit portion of the first address and a reversed low order n-bit portion of the second address.
4 . The method of claim 1 , wherein the first address is an X address in an array of pixels, and the second address is a Y address in the array of pixels.
5 . The method of claim 1 , further comprising:
generating a second cache entry number for a second pixel derived from a low order n-bit portion of a third address and a reversed low order n-bit portion of a fourth address, wherein the second cache entry number is a different number than the first cache entry number.
6 . The method of claim 1 , wherein generating a first cache entry number includes performing a bitwise operation between the low order n-bit portion of the first address and the reversed low order n-bit portion of the second address.
7 . The method of claim 1 , wherein the cache arrangement method is used for a set associative cache.
8 . The method of claim 1 , wherein reversing the order of the second n-bit portion to form a reversed n-bit portion includes reversing the order of the n+1 to the 2n bits of an address to form a reversed n-bit portion.
9 . The method of claim 8 , further comprising:
generating an intermediate cache entry number derived from the first n-bit portion and the reversed n-bit portion; and
generating a first cache entry number by performing an exclusive OR operation with an inside-out next n bits of an address.
10 . A computer-readable medium comprising instructions executable by a computing device to enable cache arrangement for graphical applications, the instructions being executable to perform a method comprising:
receiving a first address having a first n-bit portion and corresponding to a first pixel;
receiving a second address having a second n-bit portion and corresponding to the first pixel;
reversing the order of the second n-bit portion to form a reversed n-bit portion; and
generating a first cache entry number derived from the first n-bit portion and the reversed n-bit portion.
11 . The computer-readable medium of claim 10 , wherein the first n-bit portion is the low order n-bit portion of the first address and the second n-bit portion is the low order n-bit portion of the second address.
12 . The computer-readable medium of claim 10 , wherein generating a first cache entry number includes performing an exclusive OR operation between a low order n-bit portion of the first address and a reversed low order n-bit portion of the second address.
13 . The computer-readable medium of claim 10 , wherein the first address is an X address in an array of pixels, and the second address is a Y address in the array of pixels.
14 . The computer-readable medium of claim 10 , further comprising instructions for generating a second cache entry number for a second pixel derived from a low order n-bit portion of a third address and a reversed low order n-bit portion of a fourth address, wherein the second cache entry number is a different number than the first cache entry number.
15 . The computer-readable medium of claim 10 , wherein generating a first cache entry number includes performing a bitwise operation between the low order n-bit portion of the first address and the reversed low order n-bit portion of the second address.
16 . The computer-readable medium of claim 10 , wherein the cache arrangement method is used for a set associative cache.
17 . The computer-readable medium of claim 10 , wherein reversing the order of the second n-bit portion to form a reversed n-bit portion includes reversing the order of the n+1 to the 2n bits of an address to form a reversed n-bit portion.
18 . The computer-readable medium of claim 17 , further comprising instructions for:
generating an intermediate cache entry number derived from the first n-bit portion and the reversed n-bit portion; and
generating a first cache entry number by performing an exclusive OR operation with an inside-out next n bits of an address.
19 . The computer-readable medium of claim 18 , wherein the inside-out next n-bit portion is a portion of a Z address.
20 . An apparatus comprising:
a first register to receive a first address having a first n-bit portion;
a second register to receive a second address having a second n-bit portion; and
a combiner to:
reverse the order of the second n-bit portion to form a reversed n-bit portion;
generate a cache entry number derived from an exclusive OR operation between the first n-bit portion and the reversed n-bit portion; and
use the cache entry number to store data in a cache.