Semiconductor device and method for fabricating the same
View Patent ↗A semiconductor device includes: an isolation region formed in a semiconductor substrate; active regions surrounded by the isolation region and including p-type and n-type regions, respectively; an NMOS transistor formed in the active region including the p-type region and including an n-type gate electrode; a PMOS transistor formed in the active region including the n-type region and including a p-type gate electrode; and a p-type resistor formed on the isolation region. The p-type resistor has an internal stress greater than that of the p-type gate electrode.
1. A semiconductor device, comprising:
a semiconductor substrate;
an isolation region formed in the semiconductor substrate;
a first active region defined in the semiconductor substrate and surrounded by the isolation region;
a second active region defined in the semiconductor substrate and surrounded by the isolation region;
an NMOS transistor formed in the first active region and including an n-type gate electrode made of silicon doped with an n-type impurity;
a first PMOS transistor formed in the second active region and including a first p-type gate electrode made of silicon doped with a p-type impurity; and
a p-type resistor formed on the isolation region, made of silicon doped with a p-type impurity, and having an internal stress greater than that of the first p-type gate electrode.
2. The semiconductor device of claim 1 , wherein the n-type gate electrode has an internal stress that stretches, along a gate length, a channel region located under the n-type gate electrode and in a surface part of the first active region.
3. The semiconductor device of claim 1 , wherein the NMOS transistor includes a first metal silicide film formed on the n-type gate electrode, and
no metal silicide films are formed on the first p-type gate electrode and the p-type resistor.
4. The semiconductor device of claim 1 , wherein the NMOS transistor includes: a first sidewall formed on a side face of the n-type gate electrode; n-type source/drain regions defined in the first active region and located at the outside of the first sidewall; and a second metal silicide film formed on the n-type source/drain regions,
the first PMOS transistor includes: a second sidewall formed on a side face of the first p-type gate electrode; and p-type source/drain regions defined in the second active region and located at the outside of the second sidewall, and
no metal silicide film is formed on the p-type source/drain regions.
5. The semiconductor device of claim 1 , further comprising:
a third active region defined in the semiconductor substrate and surrounded by the isolation region; and
a second PMOS transistor formed in the third active region and including a second p-type gate electrode made of silicon doped with a p-type impurity and a third metal silicide film formed on the second p-type gate electrode.
6. The semiconductor device of claim 1 , wherein the p-type impurity contained in the first p-type gate electrode has an activation rate higher than that of the p-type impurity contained in the p-type resistor.
7. The semiconductor device of claim 1 , wherein a Raman spectrum to the first p-type gate electrode has a peak at a higher wavenumber than a peak of a Raman spectrum to the p-type resistor.