Lateral DMOS device and method for fabricating the same
View Patent ↗An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.
1. A method comprising:
providing a first conductivity-type semiconductor substrate having an active area and a field area; and then
forming a second conductivity-type deep well on the first conductivity-type semiconductor substrate; and then
forming a second conductivity-type adjusting layer located in the second conductivity-type deep well on the first conductivity-type semiconductor substrate; and then
forming a first conductivity-type body in the second conductivity-type deep well; and then
forming an insulating layer on the first conductivity-type semiconductor substrate in the active area and the field area; and then
forming a gate area on the first conductivity-type semiconductor substrate in the active area; and then
forming a second conductivity-type source area in the first conductivity-type body; and then
forming a second conductivity-type drain area in the second conductivity-type deep well,
wherein forming the second conductivity-type deep well comprises:
simultaneously forming a deep well cutout area by coating the first conductivity-type semiconductor substrate with a mask when performing the ion implantation for forming the second conductivity-type deep well,
wherein the second conductivity-type adjusting layer is formed on both the deep well cutout area and the second conductivity-type deep well,
wherein a thickness of a second conductivity-type epitaxial layer is increased to have a thickness of between approximately 7.5 to 8.0 μm and a width of the deep well cutout area is widened to have a width of between approximately 3 to 5 μm so as to raise a breakdown voltage and the second conductivity-type adjusting layer is added so as to lower an on-resistance of an LDMOS device.
2. The method of claim 1 , wherein forming the second conductivity-type deep well comprises:
performing ion implantation using an impurity.
3. The method of claim 1 , wherein forming the second conductivity-type adjusting layer comprises:
performing ion implantation using an impurity; and then
performing a diffusion process.
4. The method of claim 1 , further comprising, before forming the second conductivity-type deep well and the second conductivity-type adjusting layer:
forming a second conductivity-type buried layer on the first conductivity-type semiconductor substrate.
5. The method of claim 1 , further comprising, before forming the second conductivity-type deep well:
forming a first conductivity-type epitaxial layer on the first conductivity-type semiconductor substrate.
6. The method of claim 1 , wherein forming the second conductivity-type deep well comprises:
performing ion implantation using arsenic.
7. The method of claim 1 , wherein forming the second conductivity-type adjusting layer comprises:
performing ion implantation using phosphorous.
8. The method of claim 1 , wherein forming the first conductivity-type body comprises:
performing ion implantation using boron using a photoresist; and then
performing a hard bake process without removing the photoresist; and then
performing ion implantation using arsenic.
9. An apparatus comprising:
a first conductivity-type semiconductor substrate having an active area and a field area;
a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate;
a second conductivity-type adjusting layer located in the second conductivity-type deep well;
a first conductivity-type body formed in the second conductivity-type deep well;
an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area;
a gate area formed on the first conductivity-type semiconductor substrate in the active area;
a second conductivity-type source area formed in the first conductivity-type body;
a second conductivity-type drain area formed in the second conductivity-type deep well; and
a deep well cutout area formed in the second conductivity type well and under the second conductivity-type source area except under the second conductivity-type drain area
wherein the second conductivity-type adjusting layer is formed on both the deep well cutout area and the second conductivity-type deep well,
wherein a thickness of a second conductivity-type epitaxial layer is increased to have a thickness of between approximately 7.5 to 8.0 μm and a width of the deep well cutout area is widened to have a width of between approximately 3 to 5 μm so as to raise a breakdown voltage and the second conductivity-type adjusting layer is added so as to lower an on-resistance of an LDMOS device.
10. The apparatus of claim 9 , further comprising a second conductivity-type buried layer formed below the second conductivity-type deep well.
11. The apparatus of claim 9 , wherein the deep well cutout area has a width of between 3 to 5 μm.
12. The apparatus of claim 9 , wherein the deep well cutout area has a width of 4 μm.
13. The apparatus of claim 9 , further comprising a first conductivity-type epitaxial layer formed on the first conductivity-type semiconductor substrate.
14. The apparatus of claim 13 , wherein the first conductivity-type epitaxial layer has a thickness of between 7.5 to 8.0 μm.
15. The apparatus of claim 9 , wherein the second conductivity-type deep well is formed of arsenic ions.
16. The apparatus of claim 9 , wherein the second conductivity-type adjusting layer is formed of phosphorous ions.
17. The apparatus of claim 9 , wherein the first conductivity-type body is formed of implanted boron ions and arsenic ions.
18. The apparatus of claim 9 , wherein the apparatus comprises the LMDOS device having a breakdown voltage of 100V and an operation voltage of 85V.