System, method and apparatus for sensitivity based fast power grid simulation with variable time step

1. A method of analyzing a power grid in an integrated circuit comprising:

inputting a circuit design to a test bench;

inputting a plurality of initial values for the circuit design in to the test bench;

setting a current time t to 0 value for an initial time (t 0 ) of the operation of the circuit design;

representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model;

describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations;

storing the plurality of linear equations in a matrix Y 0 for time t 0 ;

resolving the matrix Y 0 to determine a DC operating point;

updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t 1 =t+h where h is a time step value equal to the current time t and a next simulated operation time;

storing the updated plurality of linear equations in a matrix Y 1 for time t 1 ;

inverting the matrix Y 1 to form inverted matrix Y 1 −1 ;

resolving the inverted matrix Y 1 −1 ;

calculating a new time step and setting the current time t to t+h;

comparing the new time step h to a plurality of time steps in a time step database;

selecting one of the plurality of time steps substantially equal to the new time step; and

recalling a solution corresponding to the selected time step.

2. The method of claim 1 , wherein comparing the new time step h to the plurality of time steps in the time step database includes calculating a time step difference.

3. The method of claim 2 , wherein calculating the time step difference includes selecting a local truncation error.

4. The method of claim 3 , wherein calculating the time step difference further includes:

determining a difference between each one of the plurality of time steps and the current time step; and

selecting one of the plurality of time steps that has a corresponding difference less than or equal the local truncation error.

5. The method of claim 1 , wherein recalling the solution corresponding to the selected time step includes resolving the matrix using the recalled solution.

6. A method of analyzing a power grid in an integrated circuit comprising:

inputting a circuit design to a test bench;

inputting a plurality of initial values for the circuit design in to the test bench;

setting a current time t to 0 value for an initial time (t 0 ) of the operation of the circuit design;

representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model;

describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations;

storing the plurality of linear equations in a matrix Y 0 for time t 0 ;

resolving the matrix Y 0 to determine a DC operating point;

updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t 1 =t+h where h is a time step value equal to the current time t and a next simulated operation time;

storing the updated plurality of linear equations in a matrix Y 1 for time t 1 ;

inverting the matrix Y 1 to form inverted matrix Y 1 −1 ;

resolving the inverted matrix Y 1 −1 ;

calculating a new time step and setting the current time t to t+h;

comparing the new time step h to a plurality of time steps in a time step database including:

calculating a time step difference;

selecting a local truncation error;

determining a difference between each one of the plurality of time steps and the current time step; and

selecting one of the plurality of time steps that has a corresponding difference less than or equal the local truncation error;

selecting one of the plurality of time steps substantially equal to the new time step;

recalling a solution corresponding to the selected time step; and

resolving the matrix using the recalled solution.

7. A system for analyzing a power grid in an integrated circuit comprising:

a computer;

computer readable logic for inputting a circuit design to the computer;

computer readable logic for inputting a plurality of initial values for the circuit design in to the test bench;

computer readable logic for setting a current time t to 0 value for an initial time (t 0 ) of the operation of the circuit design;

computer readable logic for representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model;

computer readable logic for describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations;

computer readable logic for storing the plurality of linear equations in a matrix Y 0 for time t 0 ;

computer readable logic for resolving the matrix Y 0 to determine a DC operating point;

computer readable logic for updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t 1 =t+h where h is a time step value equal to the current time t and a next simulated operation time;

computer readable logic for storing the updated plurality of linear equations in a matrix Y 1 for time t 1 ;

computer readable logic for inverting the matrix Y 1 to form inverted matrix Y 1 −1 ;

computer readable logic for resolving the inverted matrix Y 1 −1 ;

computer readable logic for calculating a new time step and setting the current time t to t+h;

computer readable logic for comparing the new time step h to a plurality of time steps in a time step database;

computer readable logic for selecting one of the plurality of time steps substantially equal to the new time step; and

computer readable logic for recalling a solution corresponding to the selected time step.

8. The system of claim 7 , wherein the computer readable logic for comparing the new time step h to the plurality of time steps in the time step database includes computer readable logic for calculating a time step difference.

9. The system of claim 8 , wherein the computer readable logic for calculating the time step difference includes the computer readable logic for selecting a local truncation error.

10. The system of claim 9 , wherein the computer readable logic for calculating the time step difference further includes:

computer readable logic for determining a difference between each one of the plurality of time steps and the current time step; and

computer readable logic for selecting one of the plurality of time steps that has a corresponding difference less than or equal the local truncation error.

11. The system of claim 7 , wherein the computer readable logic for recalling the solution corresponding to the selected time step includes computer readable logic for resolving the matrix using the recalled solution.