System and method for adapting video decoding rate
View Patent ↗An embodiment of the present invention provides systems and methods for adaptive video decoding. An example method includes determining that a video decoding rate of received video input is to be reduced, and receiving video input comprising a first and a second plurality of pictures. The method also includes reducing the video decoding rate while maintaining synchronization with an unmodified audio decoding rate, responsive to the determining that the video decoding rate of the received video input is to be reduced. The reducing includes foregoing decoding the first plurality of pictures and decoding the second plurality of pictures.
1. A method video decoding method performed by a processor comprising the steps of:
determining that a video decoding rate of received video input is to be reduced;
receiving video input comprising a first and a second plurality of pictures; and
responsive to the determining that the video decoding rate of the received video input is to be reduced, reducing the video decoding rate while maintaining synchronization with an unmodified audio decoding rate, including:
foregoing decoding the first plurality of pictures; and
decoding by a video decoder the second plurality of pictures.
2. The method of claim 1 , wherein the reducing step further comprises repeating presentations of decoded pictures in place of the first plurality of pictures in which decoding was foregone.
3. The method of claim 1 , wherein the reducing step includes maintaining existing resource priorities in controlling devices using the resources.
4. The method of claim 1 wherein the reducing step includes continuing to present audio at a regular rate and maintaining audio and video synchronization while the video decoding rate is reduced.
5. The method of claim 1 , wherein the determining step is responsive to a step of determining that at least one resource is constrained.
6. The method of claim 1 , wherein the determining step includes determining that the video decoding rate is to be reduced responsive to inadequate memory availability.
7. The method of claim 1 , wherein the determining step includes determining that the video decoding rate is to be reduced responsive to inadequate bus bandwidth availability.
8. The method of claim 1 , further comprising a step of terminating the reduced video decoding rate responsive to determining adequate resource availability.
9. The DHCT of claim 1 , wherein the processor is further configured to determine that the video decoding rate is to be reduced when at least one resource is constrained.
10. The DHCT of claim 1 , wherein the processor is further configured to determine that the video decoding rate is to be reduced when inadequate memory is available.
11. The DHCT of claim 1 , wherein the processor is further configured to determine that the video decoding rate is to be reduced when inadequate bus bandwidth is available.
12. A video decoding system for adapting to resource constraints, the system comprising:
a processor configured to;
determine that a video decoding rate of received video input is to be reduced while maintaining synchronization with an unmodified audio decoding rate;
receive video input comprising a first and second plurality of pictures; and
reduce the video decoding rate and maintain the synchronization; and
a video decoder
configured to forego decoding the first plurality of pictures; and
decode the second plurality of pictures, wherein the reduction in the video decoding rate is responsive to the determination by the processor.
13. The system of claim 12 , wherein the decode rate reduction logic further comprises repeating logic configured to repeat presentations of decoded pictures in place of the first plurality of pictures in which decoding was foregone.
14. The system of claim 12 , wherein the decode rate reduction logic further comprises audio presentation logic configured to continue presentation of audio at a regular rate and to maintain audio and video synchronization as long as the video decoding rate is reduced.
15. The system of claim 12 , further comprising constraint determination logic configured to determine that at least one resource is constrained, wherein the decode rate determination logic is responsive to the constraint determination logic.
16. The system of claim 12 , wherein the decode rate determination logic is responsive to inadequate memory availability.
17. The system of claim 12 , wherein the decode rate determination logic is responsive to inadequate bus bandwidth availability.
18. The system of claim 12 , further comprising termination logic configured to terminate the reduced video decoding rate responsive to determining adequate resource availability.
19. A digital home communication terminal (DHCT) comprising:
memory; and
a processor configured to:
determine that a video decoding rate of received video input is to be reduced while maintaining synchronization with an unmodified audio decoding rate;
receive video input comprising a first and second plurality of pictures; and
reduce the video decoding rate and maintain the synchronization, responsive determining that a video decoding rate is to be reduced, by foregoing decoding the first plurality of pictures and decoding the second plurality of pictures.
20. The DHCT of claim 19 , wherein the processor is further configured to repeat presentations of decoded pictures in place of the first plurality of pictures in which decoding was foregone.