Detecting startup fault of SDRAM voltage regulator
View Patent ↗A digital device is disclosed comprising a memory, a microprocessor operable to access the memory, and a voltage regulator for ramping an output voltage supplied to the memory during a startup operation. During the startup operation, control circuitry monitors the output voltage, and when the output voltage remains above a first threshold for a predetermined interval, sets a flag. Thereafter, the voltage regulator is enabled to ramp the output voltage after the predetermined interval.
1. A digital device comprising:
a memory;
a microprocessor operable to access the memory;
a voltage regulator for ramping an output voltage supplied to the memory during a startup operation; and
control circuitry operable to startup the digital device by:
monitoring the output voltage;
when the output voltage remains above a first threshold for a predetermined interval, setting a flag; and
enabling the voltage regulator to ramp the output voltage after the predetermined interval.
2. The digital device as recited in claim 1 , wherein:
the digital device receives a supply voltage; and
the control circuitry executes the startup operation after the supply voltage exceeds a second threshold.
3. The digital device as recited in claim 2 , wherein the supply voltage is received from a host.
4. The digital device as recited in claim 3 , further comprising a disk and a head actuated over the disk.
5. The digital device as recited in claim 1 , wherein the control circuitry enables the microprocessor after the predetermined interval.
6. The digital device as recited in claim 5 , wherein the microprocessor examines the flag to determine whether the memory started normally.
7. The digital device as recited in claim 6 , wherein when the flag is set, the microprocessor executes a test procedure to determine whether the memory started normally.
8. The digital device as recited in claim 6 , wherein the microprocessor notifies a host when the flag is set.
9. The digital device as recited in claim 7 , wherein the microprocessor notifies a host when the test procedure fails.
10. The digital device as recited in claim 1 , wherein the control circuitry is further operable to apply a load to the output voltage during the predetermined interval.
11. The digital device as recited in claim 10 , wherein the control circuitry is further operable to remove the load from the output voltage after the output voltage falls below the first threshold.
12. The digital device as recited in claim 1 , wherein the memory comprises a synchronous dynamic random access memory (SDRAM).
13. A method of starting a digital device, the digital device comprising a memory, a microprocessor operable to access the memory, and a voltage regulator for ramping an output voltage supplied to the memory during a startup operation, the method comprising:
monitoring the output voltage;
when the output voltage remains above a first threshold for a predetermined interval, setting a flag; and
enabling the voltage regulator to ramp the output voltage after the predetermined interval.
14. The method as recited in claim 13 , wherein the digital device receives a supply voltage, further comprising the step of starting the digital device after the supply voltage exceeds a second threshold.
15. The method as recited in claim 14 , wherein the supply voltage is received from a host.
16. The method as recited in claim 15 , wherein the digital device further comprises a disk and a head actuated over the disk.
17. The method as recited in claim 13 , further comprising enabling the microprocessor after the predetermined interval.
18. The method as recited in claim 13 , further comprising evaluating the flag to determine whether the memory started normally.
19. The method as recited in claim 18 , wherein when the flag is set, further comprising executing a test procedure to determine whether the memory started normally.
20. The method as recited in claim 18 , further comprising notifying a host when the flag is set.
21. The method as recited in claim 19 , further comprising notifying a host when the test procedure fails.
22. The method as recited in claim 13 , further comprising applying a load to the output voltage during the predetermined interval.
23. The method as recited in claim 22 , further comprising removing the load from the output voltage after the output voltage falls below the first threshold.
24. The method as recited in claim 13 , wherein the memory comprises a synchronous dynamic random access memory (SDRAM).
25. A disk drive comprising:
a disk;
a head actuated over the disk;
a memory;
a microprocessor operable to access the memory;
a voltage regulator for ramping an output voltage supplied to the memory during a startup operation; and
control circuitry operable to startup the disk drive by:
monitoring the output voltage;
when the output voltage remains above a first threshold for a predetermined interval, setting a flag; and
enabling the voltage regulator to ramp the output voltage after the predetermined interval.